1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tiago Vignatti <tiago.vignatti at intel.com>
25 */
26
27 #include <errno.h>
28 #include <limits.h>
29 #include <stdbool.h>
30 #include <stdio.h>
31 #include <string.h>
32
33 #include "drmtest.h"
34 #include "igt_debugfs.h"
35 #include "igt_kms.h"
36 #include "intel_chipset.h"
37 #include "ioctl_wrappers.h"
38 #include "igt_aux.h"
39
40 IGT_TEST_DESCRIPTION(
41 "Use the display CRC support to validate mmap write to an already uncached future scanout buffer.");
42
43 #define ROUNDS 10
44
45 typedef struct {
46 int drm_fd;
47 igt_display_t display;
48 struct igt_fb fb[2];
49 igt_output_t *output;
50 igt_plane_t *primary;
51 enum pipe pipe;
52 igt_crc_t ref_crc;
53 igt_pipe_crc_t *pipe_crc;
54 uint32_t devid;
55 } data_t;
56
57 static int ioctl_sync = true;
58 int dma_buf_fd;
59
dmabuf_mmap_framebuffer(int drm_fd,struct igt_fb * fb)60 static char *dmabuf_mmap_framebuffer(int drm_fd, struct igt_fb *fb)
61 {
62 char *ptr = NULL;
63
64 dma_buf_fd = prime_handle_to_fd_for_mmap(drm_fd, fb->gem_handle);
65 igt_skip_on(dma_buf_fd == -1 && errno == EINVAL);
66
67 ptr = mmap(NULL, fb->size, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0);
68 igt_assert(ptr != MAP_FAILED);
69
70 return ptr;
71 }
72
test(data_t * data)73 static void test(data_t *data)
74 {
75 igt_display_t *display = &data->display;
76 igt_output_t *output = data->output;
77 struct igt_fb *fb = &data->fb[1];
78 drmModeModeInfo *mode;
79 cairo_t *cr;
80 char *ptr;
81 uint32_t caching;
82 void *buf;
83 igt_crc_t crc;
84
85 mode = igt_output_get_mode(output);
86
87 /* create a non-white fb where we can write later */
88 igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
89 DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE, fb);
90
91 ptr = dmabuf_mmap_framebuffer(data->drm_fd, fb);
92
93 cr = igt_get_cairo_ctx(data->drm_fd, fb);
94 igt_paint_test_pattern(cr, fb->width, fb->height);
95 igt_put_cairo_ctx(data->drm_fd, fb, cr);
96
97 /* flip to it to make it UC/WC and fully flushed */
98 igt_plane_set_fb(data->primary, fb);
99 igt_display_commit(display);
100
101 /* flip back the original white buffer */
102 igt_plane_set_fb(data->primary, &data->fb[0]);
103 igt_display_commit(display);
104
105 /* make sure caching mode has become UC/WT */
106 caching = gem_get_caching(data->drm_fd, fb->gem_handle);
107 igt_assert(caching == I915_CACHING_NONE || caching == I915_CACHING_DISPLAY);
108
109 /*
110 * firstly demonstrate the need for DMA_BUF_SYNC_START ("begin_cpu_access")
111 */
112 if (ioctl_sync)
113 prime_sync_start(dma_buf_fd, true);
114
115 /* use dmabuf pointer to make the other fb all white too */
116 buf = malloc(fb->size);
117 igt_assert(buf != NULL);
118 memset(buf, 0xff, fb->size);
119 memcpy(ptr, buf, fb->size);
120 free(buf);
121
122 /* and flip to it */
123 igt_plane_set_fb(data->primary, fb);
124 igt_display_commit(display);
125
126 /* check that the crc is as expected, which requires that caches got flushed */
127 igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
128 igt_assert_crc_equal(&crc, &data->ref_crc);
129
130 /*
131 * now demonstrates the need for DMA_BUF_SYNC_END ("end_cpu_access")
132 */
133
134 /* start over, writing non-white to the fb again and flip to it to make it
135 * fully flushed */
136 cr = igt_get_cairo_ctx(data->drm_fd, fb);
137 igt_paint_test_pattern(cr, fb->width, fb->height);
138 igt_put_cairo_ctx(data->drm_fd, fb, cr);
139
140 igt_plane_set_fb(data->primary, fb);
141 igt_display_commit(display);
142
143 /* sync start, to move to CPU domain */
144 if (ioctl_sync)
145 prime_sync_start(dma_buf_fd, true);
146
147 /* use dmabuf pointer in the same fb to make it all white */
148 buf = malloc(fb->size);
149 igt_assert(buf != NULL);
150 memset(buf, 0xff, fb->size);
151 memcpy(ptr, buf, fb->size);
152 free(buf);
153
154 /* if we don't change to the GTT domain again, the whites won't get flushed
155 * and therefore we demonstrates the need for sync end here */
156 if (ioctl_sync)
157 prime_sync_end(dma_buf_fd, true);
158
159 do_or_die(drmModeDirtyFB(data->drm_fd, fb->fb_id, NULL, 0));
160
161 /* check that the crc is as expected, which requires that caches got flushed */
162 igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
163 igt_assert_crc_equal(&crc, &data->ref_crc);
164 }
165
prepare_crtc(data_t * data)166 static void prepare_crtc(data_t *data)
167 {
168 igt_display_t *display = &data->display;
169 igt_output_t *output = data->output;
170 drmModeModeInfo *mode;
171
172 /* select the pipe we want to use */
173 igt_output_set_pipe(output, data->pipe);
174
175 mode = igt_output_get_mode(output);
176
177 /* create a white reference fb and flip to it */
178 igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
179 DRM_FORMAT_XRGB8888, LOCAL_DRM_FORMAT_MOD_NONE,
180 1.0, 1.0, 1.0, &data->fb[0]);
181
182 data->primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
183
184 igt_plane_set_fb(data->primary, &data->fb[0]);
185 igt_display_commit(display);
186
187 if (data->pipe_crc)
188 igt_pipe_crc_free(data->pipe_crc);
189
190 data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe,
191 INTEL_PIPE_CRC_SOURCE_AUTO);
192
193 /* get reference crc for the white fb */
194 igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
195 }
196
cleanup_crtc(data_t * data)197 static void cleanup_crtc(data_t *data)
198 {
199 igt_display_t *display = &data->display;
200 igt_output_t *output = data->output;
201
202 igt_pipe_crc_free(data->pipe_crc);
203 data->pipe_crc = NULL;
204
205 igt_plane_set_fb(data->primary, NULL);
206
207 igt_output_set_pipe(output, PIPE_ANY);
208 igt_display_commit(display);
209
210 igt_remove_fb(data->drm_fd, &data->fb[0]);
211 igt_remove_fb(data->drm_fd, &data->fb[1]);
212 }
213
run_test(data_t * data)214 static void run_test(data_t *data)
215 {
216 igt_display_t *display = &data->display;
217 igt_output_t *output;
218 enum pipe pipe;
219
220 for_each_pipe_with_valid_output(display, pipe, output) {
221 data->output = output;
222 data->pipe = pipe;
223
224 prepare_crtc(data);
225 test(data);
226 cleanup_crtc(data);
227
228 /* once is enough */
229 return;
230 }
231
232 igt_skip("no valid crtc/connector combinations found\n");
233 }
234
235 struct igt_helper_process hog;
236
237 /**
238 * fork_cpuhog_helper:
239 *
240 * Fork a child process that loops indefinitely to consume CPU. This is used to
241 * fill the CPU caches with random information so they can get stalled,
242 * provoking incoherency with the GPU most likely.
243 */
fork_cpuhog_helper(void)244 static void fork_cpuhog_helper(void)
245 {
246 igt_fork_helper(&hog) {
247 while (1) {
248 usleep(10); /* quite ramdom really. */
249
250 if ((int)getppid() == 1) /* Parent has died, so must we. */
251 exit(0);
252 }
253 }
254 }
255
opt_handler(int opt,int opt_index,void * data)256 static int opt_handler(int opt, int opt_index, void *data)
257 {
258 if (opt == 'n') {
259 ioctl_sync = false;
260 igt_info("set via cmd line to not use sync ioctls\n");
261 } else {
262 return IGT_OPT_HANDLER_ERROR;
263 }
264
265 return IGT_OPT_HANDLER_SUCCESS;
266 }
267
268 static data_t data;
269
270 igt_main_args("n", NULL, NULL, opt_handler, NULL)
271 {
272 int i;
273
274 igt_skip_on_simulation();
275
276 igt_fixture {
277 data.drm_fd = drm_open_driver_master(DRIVER_INTEL);
278
279 data.devid = intel_get_drm_devid(data.drm_fd);
280
281 kmstest_set_vt_graphics_mode();
282
283 igt_require_pipe_crc(data.drm_fd);
284
285 igt_display_require(&data.display, data.drm_fd);
286
287 fork_cpuhog_helper();
288 }
289
290 igt_subtest("main") {
291 igt_info("Using %d rounds for the test\n", ROUNDS);
292
293 for (i = 0; i < ROUNDS; i++)
294 run_test(&data);
295 }
296
297 igt_fixture {
298 igt_display_fini(&data.display);
299
300 igt_stop_helper(&hog);
301 }
302 }
303