1 //===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef ARM_DWARF_Registers_h_ 10 #define ARM_DWARF_Registers_h_ 11 12 enum { 13 dwarf_r0 = 0, 14 dwarf_r1, 15 dwarf_r2, 16 dwarf_r3, 17 dwarf_r4, 18 dwarf_r5, 19 dwarf_r6, 20 dwarf_r7, 21 dwarf_r8, 22 dwarf_r9, 23 dwarf_r10, 24 dwarf_r11, 25 dwarf_r12, 26 dwarf_sp, 27 dwarf_lr, 28 dwarf_pc, 29 dwarf_cpsr, 30 31 dwarf_s0 = 64, 32 dwarf_s1, 33 dwarf_s2, 34 dwarf_s3, 35 dwarf_s4, 36 dwarf_s5, 37 dwarf_s6, 38 dwarf_s7, 39 dwarf_s8, 40 dwarf_s9, 41 dwarf_s10, 42 dwarf_s11, 43 dwarf_s12, 44 dwarf_s13, 45 dwarf_s14, 46 dwarf_s15, 47 dwarf_s16, 48 dwarf_s17, 49 dwarf_s18, 50 dwarf_s19, 51 dwarf_s20, 52 dwarf_s21, 53 dwarf_s22, 54 dwarf_s23, 55 dwarf_s24, 56 dwarf_s25, 57 dwarf_s26, 58 dwarf_s27, 59 dwarf_s28, 60 dwarf_s29, 61 dwarf_s30, 62 dwarf_s31, 63 64 // FPA Registers 0-7 65 dwarf_f0 = 96, 66 dwarf_f1, 67 dwarf_f2, 68 dwarf_f3, 69 dwarf_f4, 70 dwarf_f5, 71 dwarf_f6, 72 dwarf_f7, 73 74 // Intel wireless MMX general purpose registers 0 - 7 75 dwarf_wCGR0 = 104, 76 dwarf_wCGR1, 77 dwarf_wCGR2, 78 dwarf_wCGR3, 79 dwarf_wCGR4, 80 dwarf_wCGR5, 81 dwarf_wCGR6, 82 dwarf_wCGR7, 83 84 // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7) 85 dwarf_ACC0 = 104, 86 dwarf_ACC1, 87 dwarf_ACC2, 88 dwarf_ACC3, 89 dwarf_ACC4, 90 dwarf_ACC5, 91 dwarf_ACC6, 92 dwarf_ACC7, 93 94 // Intel wireless MMX data registers 0 - 15 95 dwarf_wR0 = 112, 96 dwarf_wR1, 97 dwarf_wR2, 98 dwarf_wR3, 99 dwarf_wR4, 100 dwarf_wR5, 101 dwarf_wR6, 102 dwarf_wR7, 103 dwarf_wR8, 104 dwarf_wR9, 105 dwarf_wR10, 106 dwarf_wR11, 107 dwarf_wR12, 108 dwarf_wR13, 109 dwarf_wR14, 110 dwarf_wR15, 111 112 dwarf_spsr = 128, 113 dwarf_spsr_fiq, 114 dwarf_spsr_irq, 115 dwarf_spsr_abt, 116 dwarf_spsr_und, 117 dwarf_spsr_svc, 118 119 dwarf_r8_usr = 144, 120 dwarf_r9_usr, 121 dwarf_r10_usr, 122 dwarf_r11_usr, 123 dwarf_r12_usr, 124 dwarf_r13_usr, 125 dwarf_r14_usr, 126 dwarf_r8_fiq, 127 dwarf_r9_fiq, 128 dwarf_r10_fiq, 129 dwarf_r11_fiq, 130 dwarf_r12_fiq, 131 dwarf_r13_fiq, 132 dwarf_r14_fiq, 133 dwarf_r13_irq, 134 dwarf_r14_irq, 135 dwarf_r13_abt, 136 dwarf_r14_abt, 137 dwarf_r13_und, 138 dwarf_r14_und, 139 dwarf_r13_svc, 140 dwarf_r14_svc, 141 142 // Intel wireless MMX control register in co-processor 0 - 7 143 dwarf_wC0 = 192, 144 dwarf_wC1, 145 dwarf_wC2, 146 dwarf_wC3, 147 dwarf_wC4, 148 dwarf_wC5, 149 dwarf_wC6, 150 dwarf_wC7, 151 152 // VFP-v3/Neon 153 dwarf_d0 = 256, 154 dwarf_d1, 155 dwarf_d2, 156 dwarf_d3, 157 dwarf_d4, 158 dwarf_d5, 159 dwarf_d6, 160 dwarf_d7, 161 dwarf_d8, 162 dwarf_d9, 163 dwarf_d10, 164 dwarf_d11, 165 dwarf_d12, 166 dwarf_d13, 167 dwarf_d14, 168 dwarf_d15, 169 dwarf_d16, 170 dwarf_d17, 171 dwarf_d18, 172 dwarf_d19, 173 dwarf_d20, 174 dwarf_d21, 175 dwarf_d22, 176 dwarf_d23, 177 dwarf_d24, 178 dwarf_d25, 179 dwarf_d26, 180 dwarf_d27, 181 dwarf_d28, 182 dwarf_d29, 183 dwarf_d30, 184 dwarf_d31, 185 186 // Neon quadword registers 187 dwarf_q0 = 288, 188 dwarf_q1, 189 dwarf_q2, 190 dwarf_q3, 191 dwarf_q4, 192 dwarf_q5, 193 dwarf_q6, 194 dwarf_q7, 195 dwarf_q8, 196 dwarf_q9, 197 dwarf_q10, 198 dwarf_q11, 199 dwarf_q12, 200 dwarf_q13, 201 dwarf_q14, 202 dwarf_q15 203 }; 204 205 #endif // ARM_DWARF_Registers_h_ 206