1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/Support/Alignment.h"
20 #include "llvm/Support/LowLevelTypeImpl.h"
21 #include <cstdint>
22 
23 namespace llvm {
24 
25 class AnalysisUsage;
26 class MachineFunction;
27 class MachineInstr;
28 class MachineOperand;
29 class MachineOptimizationRemarkEmitter;
30 class MachineOptimizationRemarkMissed;
31 struct MachinePointerInfo;
32 class MachineRegisterInfo;
33 class MCInstrDesc;
34 class RegisterBankInfo;
35 class TargetInstrInfo;
36 class TargetLowering;
37 class TargetPassConfig;
38 class TargetRegisterInfo;
39 class TargetRegisterClass;
40 class ConstantFP;
41 class APFloat;
42 
43 /// Try to constrain Reg to the specified register class. If this fails,
44 /// create a new virtual register in the correct class.
45 ///
46 /// \return The virtual register constrained to the right register class.
47 Register constrainRegToClass(MachineRegisterInfo &MRI,
48                              const TargetInstrInfo &TII,
49                              const RegisterBankInfo &RBI, Register Reg,
50                              const TargetRegisterClass &RegClass);
51 
52 /// Constrain the Register operand OpIdx, so that it is now constrained to the
53 /// TargetRegisterClass passed as an argument (RegClass).
54 /// If this fails, create a new virtual register in the correct class and
55 /// insert a COPY before \p InsertPt if it is a use or after if it is a
56 /// definition. The debug location of \p InsertPt is used for the new copy.
57 ///
58 /// \return The virtual register constrained to the right register class.
59 Register constrainOperandRegClass(const MachineFunction &MF,
60                                   const TargetRegisterInfo &TRI,
61                                   MachineRegisterInfo &MRI,
62                                   const TargetInstrInfo &TII,
63                                   const RegisterBankInfo &RBI,
64                                   MachineInstr &InsertPt,
65                                   const TargetRegisterClass &RegClass,
66                                   const MachineOperand &RegMO);
67 
68 /// Try to constrain Reg so that it is usable by argument OpIdx of the
69 /// provided MCInstrDesc \p II. If this fails, create a new virtual
70 /// register in the correct class and insert a COPY before \p InsertPt
71 /// if it is a use or after if it is a definition.
72 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
73 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
74 /// InsertPt is used for the new copy.
75 ///
76 /// \return The virtual register constrained to the right register class.
77 Register constrainOperandRegClass(const MachineFunction &MF,
78                                   const TargetRegisterInfo &TRI,
79                                   MachineRegisterInfo &MRI,
80                                   const TargetInstrInfo &TII,
81                                   const RegisterBankInfo &RBI,
82                                   MachineInstr &InsertPt, const MCInstrDesc &II,
83                                   const MachineOperand &RegMO, unsigned OpIdx);
84 
85 /// Mutate the newly-selected instruction \p I to constrain its (possibly
86 /// generic) virtual register operands to the instruction's register class.
87 /// This could involve inserting COPYs before (for uses) or after (for defs).
88 /// This requires the number of operands to match the instruction description.
89 /// \returns whether operand regclass constraining succeeded.
90 ///
91 // FIXME: Not all instructions have the same number of operands. We should
92 // probably expose a constrain helper per operand and let the target selector
93 // constrain individual registers, like fast-isel.
94 bool constrainSelectedInstRegOperands(MachineInstr &I,
95                                       const TargetInstrInfo &TII,
96                                       const TargetRegisterInfo &TRI,
97                                       const RegisterBankInfo &RBI);
98 
99 /// Check if DstReg can be replaced with SrcReg depending on the register
100 /// constraints.
101 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
102 
103 /// Check whether an instruction \p MI is dead: it only defines dead virtual
104 /// registers, and doesn't have other side effects.
105 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
106 
107 /// Report an ISel error as a missed optimization remark to the LLVMContext's
108 /// diagnostic stream.  Set the FailedISel MachineFunction property.
109 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
110                         MachineOptimizationRemarkEmitter &MORE,
111                         MachineOptimizationRemarkMissed &R);
112 
113 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
114                         MachineOptimizationRemarkEmitter &MORE,
115                         const char *PassName, StringRef Msg,
116                         const MachineInstr &MI);
117 
118 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
119 /// diagnostic stream.
120 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
121                         MachineOptimizationRemarkEmitter &MORE,
122                         MachineOptimizationRemarkMissed &R);
123 
124 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
125 /// returns it.
126 Optional<int64_t> getConstantVRegVal(Register VReg,
127                                      const MachineRegisterInfo &MRI);
128 /// Simple struct used to hold a constant integer value and a virtual
129 /// register.
130 struct ValueAndVReg {
131   int64_t Value;
132   Register VReg;
133 };
134 /// If \p VReg is defined by a statically evaluable chain of
135 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
136 /// and that constant fits in int64_t, returns its value as well as the
137 /// virtual register defined by this G_F/CONSTANT.
138 /// When \p LookThroughInstrs == false this function behaves like
139 /// getConstantVRegVal.
140 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
141 Optional<ValueAndVReg>
142 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
143                                   bool LookThroughInstrs = true,
144                                   bool HandleFConstants = true);
145 const ConstantFP* getConstantFPVRegVal(Register VReg,
146                                        const MachineRegisterInfo &MRI);
147 
148 /// See if Reg is defined by an single def instruction that is
149 /// Opcode. Also try to do trivial folding if it's a COPY with
150 /// same types. Returns null otherwise.
151 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
152                            const MachineRegisterInfo &MRI);
153 
154 /// Simple struct used to hold a Register value and the instruction which
155 /// defines it.
156 struct DefinitionAndSourceRegister {
157   MachineInstr *MI;
158   Register Reg;
159 };
160 
161 /// Find the def instruction for \p Reg, and underlying value Register folding
162 /// away any copies.
163 Optional<DefinitionAndSourceRegister>
164 getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
165 
166 /// Find the def instruction for \p Reg, folding away any trivial copies. May
167 /// return nullptr if \p Reg is not a generic virtual register.
168 MachineInstr *getDefIgnoringCopies(Register Reg,
169                                    const MachineRegisterInfo &MRI);
170 
171 /// Find the source register for \p Reg, folding away any trivial copies. It
172 /// will be an output register of the instruction that getDefIgnoringCopies
173 /// returns. May return an invalid register if \p Reg is not a generic virtual
174 /// register.
175 Register getSrcRegIgnoringCopies(Register Reg,
176                                  const MachineRegisterInfo &MRI);
177 
178 /// Returns an APFloat from Val converted to the appropriate size.
179 APFloat getAPFloatFromSize(double Val, unsigned Size);
180 
181 /// Modify analysis usage so it preserves passes required for the SelectionDAG
182 /// fallback.
183 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
184 
185 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
186                                   const Register Op2,
187                                   const MachineRegisterInfo &MRI);
188 
189 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
190                                   uint64_t Imm, const MachineRegisterInfo &MRI);
191 
192 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
193 /// this returns if \p Val can be assumed to never be a signaling NaN.
194 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
195                      bool SNaN = false);
196 
197 /// Returns true if \p Val can be assumed to never be a signaling NaN.
isKnownNeverSNaN(Register Val,const MachineRegisterInfo & MRI)198 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
199   return isKnownNeverNaN(Val, MRI, true);
200 }
201 
202 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
203 
204 /// Return a virtual register corresponding to the incoming argument register \p
205 /// PhysReg. This register is expected to have class \p RC, and optional type \p
206 /// RegTy. This assumes all references to the register will use the same type.
207 ///
208 /// If there is an existing live-in argument register, it will be returned.
209 /// This will also ensure there is a valid copy
210 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII,
211                                   MCRegister PhysReg,
212                                   const TargetRegisterClass &RC,
213                                   LLT RegTy = LLT());
214 
215 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
216 /// number of vector elements or scalar bitwidth. The intent is a
217 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
218 /// \p OrigTy elements, and unmerged into \p TargetTy
219 LLVM_READNONE
220 LLT getLCMType(LLT OrigTy, LLT TargetTy);
221 
222 /// Return a type where the total size is the greatest common divisor of \p
223 /// OrigTy and \p TargetTy. This will try to either change the number of vector
224 /// elements, or bitwidth of scalars. The intent is the result type can be used
225 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
226 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
227 /// with intermediate casts) can re-form \p TargetTy.
228 ///
229 /// If these are vectors with different element types, this will try to produce
230 /// a vector with a compatible total size, but the element type of \p OrigTy. If
231 /// this can't be satisfied, this will produce a scalar smaller than the
232 /// original vector elements.
233 ///
234 /// In the worst case, this returns LLT::scalar(1)
235 LLVM_READNONE
236 LLT getGCDType(LLT OrigTy, LLT TargetTy);
237 
238 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
239 /// If \p MI is not a splat, returns None.
240 Optional<int> getSplatIndex(MachineInstr &MI);
241 
242 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
243 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
244                                               const MachineRegisterInfo &MRI);
245 
246 /// Return true if the specified instruction is a G_BUILD_VECTOR or
247 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
248 bool isBuildVectorAllZeros(const MachineInstr &MI,
249                            const MachineRegisterInfo &MRI);
250 
251 /// Return true if the specified instruction is a G_BUILD_VECTOR or
252 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
253 bool isBuildVectorAllOnes(const MachineInstr &MI,
254                           const MachineRegisterInfo &MRI);
255 
256 /// Returns true if given the TargetLowering's boolean contents information,
257 /// the value \p Val contains a true value.
258 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
259                     bool IsFP);
260 
261 /// Returns an integer representing true, as defined by the
262 /// TargetBooleanContents.
263 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
264 } // End namespace llvm.
265 #endif
266