1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===------------------------------------------------------------===// 8 9include "llvm/TableGen/SearchableTable.td" 10include "llvm/Target/Target.td" 11include "AMDGPUFeatures.td" 12 13def p0 : PtrValueType<i64, 0>; 14def p1 : PtrValueType<i64, 1>; 15def p2 : PtrValueType<i32, 2>; 16def p3 : PtrValueType<i32, 3>; 17def p4 : PtrValueType<i64, 4>; 18def p5 : PtrValueType<i32, 5>; 19def p6 : PtrValueType<i32, 6>; 20 21 22class BoolToList<bit Value> { 23 list<int> ret = !if(Value, [1]<int>, []<int>); 24} 25 26//===------------------------------------------------------------===// 27// Subtarget Features (device properties) 28//===------------------------------------------------------------===// 29 30def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf", 31 "FastFMAF32", 32 "true", 33 "Assuming f32 fma is at least as fast as mul + add" 34>; 35 36def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32", 37 "FastDenormalF32", 38 "true", 39 "Enabling denormals does not cause f32 instructions to run at f64 rates" 40>; 41 42def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128", 43 "MIMG_R128", 44 "true", 45 "Support 128-bit texture resources" 46>; 47 48def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops", 49 "HalfRate64Ops", 50 "true", 51 "Most fp64 instructions are half rate instead of quarter" 52>; 53 54def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space", 55 "FlatAddressSpace", 56 "true", 57 "Support flat address space" 58>; 59 60def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets", 61 "FlatInstOffsets", 62 "true", 63 "Flat instructions have immediate offset addressing mode" 64>; 65 66def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts", 67 "FlatGlobalInsts", 68 "true", 69 "Have global_* flat memory instructions" 70>; 71 72def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts", 73 "FlatScratchInsts", 74 "true", 75 "Have scratch_* flat memory instructions" 76>; 77 78def FeatureScalarFlatScratchInsts : SubtargetFeature<"scalar-flat-scratch-insts", 79 "ScalarFlatScratchInsts", 80 "true", 81 "Have s_scratch_* flat memory instructions" 82>; 83 84def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts", 85 "AddNoCarryInsts", 86 "true", 87 "Have VALU add/sub instructions without carry out" 88>; 89 90def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access", 91 "UnalignedBufferAccess", 92 "true", 93 "Hardware supports unaligned global loads and stores" 94>; 95 96def FeatureTrapHandler: SubtargetFeature<"trap-handler", 97 "TrapHandler", 98 "true", 99 "Trap handler support" 100>; 101 102def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access", 103 "UnalignedScratchAccess", 104 "true", 105 "Support unaligned scratch loads and stores" 106>; 107 108def FeatureUnalignedDSAccess : SubtargetFeature<"unaligned-ds-access", 109 "UnalignedDSAccess", 110 "true", 111 "Hardware supports unaligned local and region loads and stores" 112>; 113 114def FeatureApertureRegs : SubtargetFeature<"aperture-regs", 115 "HasApertureRegs", 116 "true", 117 "Has Memory Aperture Base and Size Registers" 118>; 119 120def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts", 121 "HasMadMixInsts", 122 "true", 123 "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions" 124>; 125 126def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts", 127 "HasFmaMixInsts", 128 "true", 129 "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions" 130>; 131 132def FeatureDoesNotSupportXNACK : SubtargetFeature<"no-xnack-support", 133 "DoesNotSupportXNACK", 134 "true", 135 "Hardware does not support XNACK" 136>; 137 138// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support 139// XNACK. The current default kernel driver setting is: 140// - graphics ring: XNACK disabled 141// - compute ring: XNACK enabled 142// 143// If XNACK is enabled, the VMEM latency can be worse. 144// If XNACK is disabled, the 2 SGPRs can be used for general purposes. 145def FeatureXNACK : SubtargetFeature<"xnack", 146 "EnableXNACK", 147 "true", 148 "Enable XNACK support" 149>; 150 151def FeatureCuMode : SubtargetFeature<"cumode", 152 "EnableCuMode", 153 "true", 154 "Enable CU wavefront execution mode" 155>; 156 157def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug", 158 "SGPRInitBug", 159 "true", 160 "VI SGPR initialization bug requiring a fixed SGPR allocation size" 161>; 162 163def FeatureLdsMisalignedBug : SubtargetFeature<"lds-misaligned-bug", 164 "LDSMisalignedBug", 165 "true", 166 "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode" 167>; 168 169def FeatureMFMAInlineLiteralBug : SubtargetFeature<"mfma-inline-literal-bug", 170 "HasMFMAInlineLiteralBug", 171 "true", 172 "MFMA cannot use inline literal as SrcC" 173>; 174 175def FeatureVcmpxPermlaneHazard : SubtargetFeature<"vcmpx-permlane-hazard", 176 "HasVcmpxPermlaneHazard", 177 "true", 178 "TODO: describe me" 179>; 180 181def FeatureVMEMtoScalarWriteHazard : SubtargetFeature<"vmem-to-scalar-write-hazard", 182 "HasVMEMtoScalarWriteHazard", 183 "true", 184 "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution." 185>; 186 187def FeatureSMEMtoVectorWriteHazard : SubtargetFeature<"smem-to-vector-write-hazard", 188 "HasSMEMtoVectorWriteHazard", 189 "true", 190 "s_load_dword followed by v_cmp page faults" 191>; 192 193def FeatureInstFwdPrefetchBug : SubtargetFeature<"inst-fwd-prefetch-bug", 194 "HasInstFwdPrefetchBug", 195 "true", 196 "S_INST_PREFETCH instruction causes shader to hang" 197>; 198 199def FeatureVcmpxExecWARHazard : SubtargetFeature<"vcmpx-exec-war-hazard", 200 "HasVcmpxExecWARHazard", 201 "true", 202 "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)" 203>; 204 205def FeatureLdsBranchVmemWARHazard : SubtargetFeature<"lds-branch-vmem-war-hazard", 206 "HasLdsBranchVmemWARHazard", 207 "true", 208 "Switching between LDS and VMEM-tex not waiting VM_VSRC=0" 209>; 210 211def FeatureNSAtoVMEMBug : SubtargetFeature<"nsa-to-vmem-bug", 212 "HasNSAtoVMEMBug", 213 "true", 214 "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero" 215>; 216 217def FeatureFlatSegmentOffsetBug : SubtargetFeature<"flat-segment-offset-bug", 218 "HasFlatSegmentOffsetBug", 219 "true", 220 "GFX10 bug, inst_offset ignored in flat segment" 221>; 222 223def FeatureOffset3fBug : SubtargetFeature<"offset-3f-bug", 224 "HasOffset3fBug", 225 "true", 226 "Branch offset of 3f hardware bug" 227>; 228 229def FeatureImageStoreD16Bug : SubtargetFeature<"image-store-d16-bug", 230 "HasImageStoreD16Bug", 231 "true", 232 "Image Store D16 hardware bug" 233>; 234 235def FeatureImageGather4D16Bug : SubtargetFeature<"image-gather4-d16-bug", 236 "HasImageGather4D16Bug", 237 "true", 238 "Image Gather4 D16 hardware bug" 239>; 240 241class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature < 242 "ldsbankcount"#Value, 243 "LDSBankCount", 244 !cast<string>(Value), 245 "The number of LDS banks per compute unit." 246>; 247 248def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>; 249def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>; 250 251def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding", 252 "GCN3Encoding", 253 "true", 254 "Encoding format for VI" 255>; 256 257def FeatureCIInsts : SubtargetFeature<"ci-insts", 258 "CIInsts", 259 "true", 260 "Additional instructions for CI+" 261>; 262 263def FeatureGFX8Insts : SubtargetFeature<"gfx8-insts", 264 "GFX8Insts", 265 "true", 266 "Additional instructions for GFX8+" 267>; 268 269def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts", 270 "GFX9Insts", 271 "true", 272 "Additional instructions for GFX9+" 273>; 274 275def FeatureGFX10Insts : SubtargetFeature<"gfx10-insts", 276 "GFX10Insts", 277 "true", 278 "Additional instructions for GFX10+" 279>; 280 281def FeatureGFX10_3Insts : SubtargetFeature<"gfx10-3-insts", 282 "GFX10_3Insts", 283 "true", 284 "Additional instructions for GFX10.3" 285>; 286 287def FeatureGFX7GFX8GFX9Insts : SubtargetFeature<"gfx7-gfx8-gfx9-insts", 288 "GFX7GFX8GFX9Insts", 289 "true", 290 "Instructions shared in GFX7, GFX8, GFX9" 291>; 292 293def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime", 294 "HasSMemRealTime", 295 "true", 296 "Has s_memrealtime instruction" 297>; 298 299def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm", 300 "HasInv2PiInlineImm", 301 "true", 302 "Has 1 / (2 * pi) as inline immediate" 303>; 304 305def Feature16BitInsts : SubtargetFeature<"16-bit-insts", 306 "Has16BitInsts", 307 "true", 308 "Has i16/f16 instructions" 309>; 310 311def FeatureVOP3P : SubtargetFeature<"vop3p", 312 "HasVOP3PInsts", 313 "true", 314 "Has VOP3P packed instructions" 315>; 316 317def FeatureMovrel : SubtargetFeature<"movrel", 318 "HasMovrel", 319 "true", 320 "Has v_movrel*_b32 instructions" 321>; 322 323def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode", 324 "HasVGPRIndexMode", 325 "true", 326 "Has VGPR mode register indexing" 327>; 328 329def FeatureScalarStores : SubtargetFeature<"scalar-stores", 330 "HasScalarStores", 331 "true", 332 "Has store scalar memory instructions" 333>; 334 335def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics", 336 "HasScalarAtomics", 337 "true", 338 "Has atomic scalar memory instructions" 339>; 340 341def FeatureSDWA : SubtargetFeature<"sdwa", 342 "HasSDWA", 343 "true", 344 "Support SDWA (Sub-DWORD Addressing) extension" 345>; 346 347def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod", 348 "HasSDWAOmod", 349 "true", 350 "Support OMod with SDWA (Sub-DWORD Addressing) extension" 351>; 352 353def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar", 354 "HasSDWAScalar", 355 "true", 356 "Support scalar register with SDWA (Sub-DWORD Addressing) extension" 357>; 358 359def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst", 360 "HasSDWASdst", 361 "true", 362 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension" 363>; 364 365def FeatureSDWAMac : SubtargetFeature<"sdwa-mav", 366 "HasSDWAMac", 367 "true", 368 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension" 369>; 370 371def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc", 372 "HasSDWAOutModsVOPC", 373 "true", 374 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension" 375>; 376 377def FeatureDPP : SubtargetFeature<"dpp", 378 "HasDPP", 379 "true", 380 "Support DPP (Data Parallel Primitives) extension" 381>; 382 383// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes. 384def FeatureDPP8 : SubtargetFeature<"dpp8", 385 "HasDPP8", 386 "true", 387 "Support DPP8 (Data Parallel Primitives) extension" 388>; 389 390def FeatureR128A16 : SubtargetFeature<"r128-a16", 391 "HasR128A16", 392 "true", 393 "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128" 394>; 395 396def FeatureGFX10A16 : SubtargetFeature<"a16", 397 "HasGFX10A16", 398 "true", 399 "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands" 400>; 401 402def FeatureG16 : SubtargetFeature<"g16", 403 "HasG16", 404 "true", 405 "Support G16 for 16-bit gradient image operands" 406>; 407 408def FeatureNSAEncoding : SubtargetFeature<"nsa-encoding", 409 "HasNSAEncoding", 410 "true", 411 "Support NSA encoding for image instructions" 412>; 413 414def FeatureGFX10_BEncoding : SubtargetFeature<"gfx10_b-encoding", 415 "GFX10_BEncoding", 416 "true", 417 "Encoding format GFX10_B" 418>; 419 420def FeatureIntClamp : SubtargetFeature<"int-clamp-insts", 421 "HasIntClamp", 422 "true", 423 "Support clamp for integer destination" 424>; 425 426def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem", 427 "HasUnpackedD16VMem", 428 "true", 429 "Has unpacked d16 vmem instructions" 430>; 431 432def FeatureDLInsts : SubtargetFeature<"dl-insts", 433 "HasDLInsts", 434 "true", 435 "Has v_fmac_f32 and v_xnor_b32 instructions" 436>; 437 438def FeatureDot1Insts : SubtargetFeature<"dot1-insts", 439 "HasDot1Insts", 440 "true", 441 "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions" 442>; 443 444def FeatureDot2Insts : SubtargetFeature<"dot2-insts", 445 "HasDot2Insts", 446 "true", 447 "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions" 448>; 449 450def FeatureDot3Insts : SubtargetFeature<"dot3-insts", 451 "HasDot3Insts", 452 "true", 453 "Has v_dot8c_i32_i4 instruction" 454>; 455 456def FeatureDot4Insts : SubtargetFeature<"dot4-insts", 457 "HasDot4Insts", 458 "true", 459 "Has v_dot2c_i32_i16 instruction" 460>; 461 462def FeatureDot5Insts : SubtargetFeature<"dot5-insts", 463 "HasDot5Insts", 464 "true", 465 "Has v_dot2c_f32_f16 instruction" 466>; 467 468def FeatureDot6Insts : SubtargetFeature<"dot6-insts", 469 "HasDot6Insts", 470 "true", 471 "Has v_dot4c_i32_i8 instruction" 472>; 473 474def FeatureMAIInsts : SubtargetFeature<"mai-insts", 475 "HasMAIInsts", 476 "true", 477 "Has mAI instructions" 478>; 479 480def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst", 481 "HasPkFmacF16Inst", 482 "true", 483 "Has v_pk_fmac_f16 instruction" 484>; 485 486def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts", 487 "HasAtomicFaddInsts", 488 "true", 489 "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, " 490 "global_atomic_pk_add_f16 instructions", 491 [FeatureFlatGlobalInsts] 492>; 493 494def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support", 495 "DoesNotSupportSRAMECC", 496 "true", 497 "Hardware does not support SRAM ECC" 498>; 499 500def FeatureSRAMECC : SubtargetFeature<"sram-ecc", 501 "EnableSRAMECC", 502 "true", 503 "Enable SRAM ECC" 504>; 505 506def FeatureNoSdstCMPX : SubtargetFeature<"no-sdst-cmpx", 507 "HasNoSdstCMPX", 508 "true", 509 "V_CMPX does not write VCC/SGPR in addition to EXEC" 510>; 511 512def FeatureVscnt : SubtargetFeature<"vscnt", 513 "HasVscnt", 514 "true", 515 "Has separate store vscnt counter" 516>; 517 518def FeatureGetWaveIdInst : SubtargetFeature<"get-wave-id-inst", 519 "HasGetWaveIdInst", 520 "true", 521 "Has s_get_waveid_in_workgroup instruction" 522>; 523 524def FeatureSMemTimeInst : SubtargetFeature<"s-memtime-inst", 525 "HasSMemTimeInst", 526 "true", 527 "Has s_memtime instruction" 528>; 529 530def FeatureMadMacF32Insts : SubtargetFeature<"mad-mac-f32-insts", 531 "HasMadMacF32Insts", 532 "true", 533 "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions" 534>; 535 536def FeatureDsSrc2Insts : SubtargetFeature<"ds-src2-insts", 537 "HasDsSrc2Insts", 538 "true", 539 "Has ds_*_src2 instructions" 540>; 541 542def FeatureRegisterBanking : SubtargetFeature<"register-banking", 543 "HasRegisterBanking", 544 "true", 545 "Has register banking" 546>; 547 548def FeatureVOP3Literal : SubtargetFeature<"vop3-literal", 549 "HasVOP3Literal", 550 "true", 551 "Can use one literal in VOP3" 552>; 553 554def FeatureNoDataDepHazard : SubtargetFeature<"no-data-dep-hazard", 555 "HasNoDataDepHazard", 556 "true", 557 "Does not need SW waitstates" 558>; 559 560//===------------------------------------------------------------===// 561// Subtarget Features (options and debugging) 562//===------------------------------------------------------------===// 563 564class FeatureMaxPrivateElementSize<int size> : SubtargetFeature< 565 "max-private-element-size-"#size, 566 "MaxPrivateElementSize", 567 !cast<string>(size), 568 "Maximum private access size may be "#size 569>; 570 571def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>; 572def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>; 573def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>; 574 575def FeatureDumpCode : SubtargetFeature <"DumpCode", 576 "DumpCode", 577 "true", 578 "Dump MachineInstrs in the CodeEmitter" 579>; 580 581def FeatureDumpCodeLower : SubtargetFeature <"dumpcode", 582 "DumpCode", 583 "true", 584 "Dump MachineInstrs in the CodeEmitter" 585>; 586 587// XXX - This should probably be removed once enabled by default 588def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt", 589 "EnableLoadStoreOpt", 590 "true", 591 "Enable SI load/store optimizer pass" 592>; 593 594// Performance debugging feature. Allow using DS instruction immediate 595// offsets even if the base pointer can't be proven to be base. On SI, 596// base pointer values that won't give the same result as a 16-bit add 597// are not safe to fold, but this will override the conservative test 598// for the base pointer. 599def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature < 600 "unsafe-ds-offset-folding", 601 "EnableUnsafeDSOffsetFolding", 602 "true", 603 "Force using DS instruction immediate offsets on SI" 604>; 605 606def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler", 607 "EnableSIScheduler", 608 "true", 609 "Enable SI Machine Scheduler" 610>; 611 612def FeatureEnableDS128 : SubtargetFeature<"enable-ds128", 613 "EnableDS128", 614 "true", 615 "Use ds_{read|write}_b128" 616>; 617 618// Sparse texture support requires that all result registers are zeroed when 619// PRTStrictNull is set to true. This feature is turned on for all architectures 620// but is enabled as a feature in case there are situations where PRTStrictNull 621// is disabled by the driver. 622def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null", 623 "EnablePRTStrictNull", 624 "true", 625 "Enable zeroing of result registers for sparse texture fetches" 626>; 627 628// Unless +-flat-for-global is specified, turn on FlatForGlobal for 629// all OS-es on VI and newer hardware to avoid assertion failures due 630// to missing ADDR64 variants of MUBUF instructions. 631// FIXME: moveToVALU should be able to handle converting addr64 MUBUF 632// instructions. 633 634def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global", 635 "FlatForGlobal", 636 "true", 637 "Force to generate flat instruction for global" 638>; 639 640def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature < 641 "auto-waitcnt-before-barrier", 642 "AutoWaitcntBeforeBarrier", 643 "true", 644 "Hardware automatically inserts waitcnt before barrier" 645>; 646 647def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range", 648 "HasTrigReducedRange", 649 "true", 650 "Requires use of fract on arguments to trig instructions" 651>; 652 653// Alignment enforcement is controlled by a configuration register: 654// SH_MEM_CONFIG.alignment_mode 655def FeatureUnalignedAccessMode : SubtargetFeature<"unaligned-access-mode", 656 "UnalignedAccessMode", 657 "true", 658 "Enable unaligned global, local and region loads and stores if the hardware" 659 " supports it" 660>; 661 662// Dummy feature used to disable assembler instructions. 663def FeatureDisable : SubtargetFeature<"", 664 "FeatureDisable","true", 665 "Dummy feature to disable assembler instructions" 666>; 667 668class GCNSubtargetFeatureGeneration <string Value, 669 string FeatureName, 670 list<SubtargetFeature> Implies> : 671 SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>; 672 673def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", 674 "southern-islands", 675 [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, 676 FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts, 677 FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel, 678 FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC, 679 FeatureDoesNotSupportXNACK] 680>; 681 682def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", 683 "sea-islands", 684 [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, 685 FeatureWavefrontSize64, FeatureFlatAddressSpace, 686 FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange, 687 FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, 688 FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, 689 FeatureUnalignedBufferAccess] 690>; 691 692def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", 693 "volcanic-islands", 694 [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, 695 FeatureWavefrontSize64, FeatureFlatAddressSpace, 696 FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, 697 FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel, 698 FeatureScalarStores, FeatureInv2PiInlineImm, 699 FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP, 700 FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts, 701 FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, 702 FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32, 703 FeatureUnalignedBufferAccess 704 ] 705>; 706 707def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9", 708 "gfx9", 709 [FeatureFP64, FeatureLocalMemorySize65536, 710 FeatureWavefrontSize64, FeatureFlatAddressSpace, 711 FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, 712 FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm, 713 FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode, 714 FeatureFastFMAF32, FeatureDPP, FeatureIntClamp, 715 FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst, 716 FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts, 717 FeatureAddNoCarryInsts, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, 718 FeatureScalarFlatScratchInsts, FeatureScalarAtomics, FeatureR128A16, 719 FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, 720 FeatureFastDenormalF32, FeatureUnalignedBufferAccess, 721 FeatureUnalignedDSAccess 722 ] 723>; 724 725def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10", 726 "gfx10", 727 [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128, 728 FeatureFlatAddressSpace, 729 FeatureCIInsts, Feature16BitInsts, 730 FeatureSMemRealTime, FeatureInv2PiInlineImm, 731 FeatureApertureRegs, FeatureGFX9Insts, FeatureGFX10Insts, FeatureVOP3P, 732 FeatureMovrel, FeatureFastFMAF32, FeatureDPP, FeatureIntClamp, 733 FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst, 734 FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts, 735 FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts, 736 FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking, 737 FeatureVOP3Literal, FeatureDPP8, 738 FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC, 739 FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16, 740 FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess 741 ] 742>; 743 744class FeatureSet<list<SubtargetFeature> Features_> { 745 list<SubtargetFeature> Features = Features_; 746} 747 748def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands, 749 FeatureFastFMAF32, 750 HalfRate64Ops, 751 FeatureLDSBankCount32, 752 FeatureDoesNotSupportXNACK]>; 753 754def FeatureISAVersion6_0_1 : FeatureSet< 755 [FeatureSouthernIslands, 756 FeatureLDSBankCount32, 757 FeatureDoesNotSupportXNACK]>; 758 759def FeatureISAVersion6_0_2 : FeatureSet< 760 [FeatureSouthernIslands, 761 FeatureLDSBankCount32, 762 FeatureDoesNotSupportXNACK]>; 763 764def FeatureISAVersion7_0_0 : FeatureSet< 765 [FeatureSeaIslands, 766 FeatureLDSBankCount32, 767 FeatureDoesNotSupportXNACK]>; 768 769def FeatureISAVersion7_0_1 : FeatureSet< 770 [FeatureSeaIslands, 771 HalfRate64Ops, 772 FeatureLDSBankCount32, 773 FeatureFastFMAF32, 774 FeatureDoesNotSupportXNACK]>; 775 776def FeatureISAVersion7_0_2 : FeatureSet< 777 [FeatureSeaIslands, 778 FeatureLDSBankCount16, 779 FeatureFastFMAF32, 780 FeatureDoesNotSupportXNACK]>; 781 782def FeatureISAVersion7_0_3 : FeatureSet< 783 [FeatureSeaIslands, 784 FeatureLDSBankCount16, 785 FeatureDoesNotSupportXNACK]>; 786 787def FeatureISAVersion7_0_4 : FeatureSet< 788 [FeatureSeaIslands, 789 FeatureLDSBankCount32, 790 FeatureDoesNotSupportXNACK]>; 791 792def FeatureISAVersion7_0_5 : FeatureSet< 793 [FeatureSeaIslands, 794 FeatureLDSBankCount16, 795 FeatureDoesNotSupportXNACK]>; 796 797def FeatureISAVersion8_0_1 : FeatureSet< 798 [FeatureVolcanicIslands, 799 FeatureFastFMAF32, 800 HalfRate64Ops, 801 FeatureLDSBankCount32, 802 FeatureXNACK, 803 FeatureUnpackedD16VMem]>; 804 805def FeatureISAVersion8_0_2 : FeatureSet< 806 [FeatureVolcanicIslands, 807 FeatureLDSBankCount32, 808 FeatureSGPRInitBug, 809 FeatureUnpackedD16VMem, 810 FeatureDoesNotSupportXNACK]>; 811 812def FeatureISAVersion8_0_3 : FeatureSet< 813 [FeatureVolcanicIslands, 814 FeatureLDSBankCount32, 815 FeatureUnpackedD16VMem, 816 FeatureDoesNotSupportXNACK]>; 817 818def FeatureISAVersion8_0_5 : FeatureSet< 819 [FeatureVolcanicIslands, 820 FeatureLDSBankCount32, 821 FeatureSGPRInitBug, 822 FeatureUnpackedD16VMem, 823 FeatureDoesNotSupportXNACK]>; 824 825def FeatureISAVersion8_1_0 : FeatureSet< 826 [FeatureVolcanicIslands, 827 FeatureLDSBankCount16, 828 FeatureXNACK, 829 FeatureImageStoreD16Bug, 830 FeatureImageGather4D16Bug]>; 831 832def FeatureISAVersion9_0_0 : FeatureSet< 833 [FeatureGFX9, 834 FeatureMadMixInsts, 835 FeatureLDSBankCount32, 836 FeatureDoesNotSupportXNACK, 837 FeatureDoesNotSupportSRAMECC, 838 FeatureImageGather4D16Bug]>; 839 840def FeatureISAVersion9_0_2 : FeatureSet< 841 [FeatureGFX9, 842 FeatureMadMixInsts, 843 FeatureLDSBankCount32, 844 FeatureXNACK, 845 FeatureDoesNotSupportSRAMECC, 846 FeatureImageGather4D16Bug]>; 847 848def FeatureISAVersion9_0_4 : FeatureSet< 849 [FeatureGFX9, 850 FeatureLDSBankCount32, 851 FeatureFmaMixInsts, 852 FeatureDoesNotSupportXNACK, 853 FeatureDoesNotSupportSRAMECC, 854 FeatureImageGather4D16Bug]>; 855 856def FeatureISAVersion9_0_6 : FeatureSet< 857 [FeatureGFX9, 858 HalfRate64Ops, 859 FeatureFmaMixInsts, 860 FeatureLDSBankCount32, 861 FeatureDLInsts, 862 FeatureDot1Insts, 863 FeatureDot2Insts, 864 FeatureDoesNotSupportXNACK, 865 FeatureImageGather4D16Bug]>; 866 867def FeatureISAVersion9_0_8 : FeatureSet< 868 [FeatureGFX9, 869 HalfRate64Ops, 870 FeatureFmaMixInsts, 871 FeatureLDSBankCount32, 872 FeatureDLInsts, 873 FeatureDot1Insts, 874 FeatureDot2Insts, 875 FeatureDot3Insts, 876 FeatureDot4Insts, 877 FeatureDot5Insts, 878 FeatureDot6Insts, 879 FeatureMAIInsts, 880 FeaturePkFmacF16Inst, 881 FeatureAtomicFaddInsts, 882 FeatureSRAMECC, 883 FeatureMFMAInlineLiteralBug, 884 FeatureImageGather4D16Bug]>; 885 886def FeatureISAVersion9_0_9 : FeatureSet< 887 [FeatureGFX9, 888 FeatureMadMixInsts, 889 FeatureLDSBankCount32, 890 FeatureXNACK, 891 FeatureImageGather4D16Bug]>; 892 893def FeatureISAVersion9_0_C : FeatureSet< 894 [FeatureGFX9, 895 FeatureMadMixInsts, 896 FeatureLDSBankCount32, 897 FeatureXNACK, 898 FeatureImageGather4D16Bug]>; 899 900// TODO: Organize more features into groups. 901def FeatureGroup { 902 // Bugs present on gfx10.1. 903 list<SubtargetFeature> GFX10_1_Bugs = [ 904 FeatureVcmpxPermlaneHazard, 905 FeatureVMEMtoScalarWriteHazard, 906 FeatureSMEMtoVectorWriteHazard, 907 FeatureInstFwdPrefetchBug, 908 FeatureVcmpxExecWARHazard, 909 FeatureLdsBranchVmemWARHazard, 910 FeatureNSAtoVMEMBug, 911 FeatureOffset3fBug, 912 FeatureFlatSegmentOffsetBug 913 ]; 914} 915 916def FeatureISAVersion10_1_0 : FeatureSet< 917 !listconcat(FeatureGroup.GFX10_1_Bugs, 918 [FeatureGFX10, 919 FeatureLDSBankCount32, 920 FeatureDLInsts, 921 FeatureNSAEncoding, 922 FeatureWavefrontSize32, 923 FeatureScalarStores, 924 FeatureScalarAtomics, 925 FeatureScalarFlatScratchInsts, 926 FeatureGetWaveIdInst, 927 FeatureSMemTimeInst, 928 FeatureMadMacF32Insts, 929 FeatureDsSrc2Insts, 930 FeatureLdsMisalignedBug, 931 FeatureDoesNotSupportXNACK])>; 932 933def FeatureISAVersion10_1_1 : FeatureSet< 934 !listconcat(FeatureGroup.GFX10_1_Bugs, 935 [FeatureGFX10, 936 FeatureLDSBankCount32, 937 FeatureDLInsts, 938 FeatureDot1Insts, 939 FeatureDot2Insts, 940 FeatureDot5Insts, 941 FeatureDot6Insts, 942 FeatureNSAEncoding, 943 FeatureWavefrontSize32, 944 FeatureScalarStores, 945 FeatureScalarAtomics, 946 FeatureScalarFlatScratchInsts, 947 FeatureGetWaveIdInst, 948 FeatureSMemTimeInst, 949 FeatureMadMacF32Insts, 950 FeatureDsSrc2Insts, 951 FeatureLdsMisalignedBug, 952 FeatureDoesNotSupportXNACK])>; 953 954def FeatureISAVersion10_1_2 : FeatureSet< 955 !listconcat(FeatureGroup.GFX10_1_Bugs, 956 [FeatureGFX10, 957 FeatureLDSBankCount32, 958 FeatureDLInsts, 959 FeatureDot1Insts, 960 FeatureDot2Insts, 961 FeatureDot5Insts, 962 FeatureDot6Insts, 963 FeatureNSAEncoding, 964 FeatureWavefrontSize32, 965 FeatureScalarStores, 966 FeatureScalarAtomics, 967 FeatureScalarFlatScratchInsts, 968 FeatureGetWaveIdInst, 969 FeatureSMemTimeInst, 970 FeatureMadMacF32Insts, 971 FeatureDsSrc2Insts, 972 FeatureLdsMisalignedBug, 973 FeatureDoesNotSupportXNACK])>; 974 975def FeatureISAVersion10_3_0 : FeatureSet< 976 [FeatureGFX10, 977 FeatureGFX10_BEncoding, 978 FeatureGFX10_3Insts, 979 FeatureLDSBankCount32, 980 FeatureDLInsts, 981 FeatureDot1Insts, 982 FeatureDot2Insts, 983 FeatureDot5Insts, 984 FeatureDot6Insts, 985 FeatureNSAEncoding, 986 FeatureWavefrontSize32, 987 FeatureDoesNotSupportXNACK]>; 988 989//===----------------------------------------------------------------------===// 990 991def AMDGPUInstrInfo : InstrInfo { 992 let guessInstructionProperties = 1; 993 let noNamedPositionallyEncodedOperands = 1; 994} 995 996def AMDGPUAsmParser : AsmParser { 997 // Some of the R600 registers have the same name, so this crashes. 998 // For example T0_XYZW and T0_XY both have the asm name T0. 999 let ShouldEmitMatchRegisterName = 0; 1000} 1001 1002def AMDGPUAsmWriter : AsmWriter { 1003 int PassSubtarget = 1; 1004} 1005 1006def AMDGPUAsmVariants { 1007 string Default = "Default"; 1008 int Default_ID = 0; 1009 string VOP3 = "VOP3"; 1010 int VOP3_ID = 1; 1011 string SDWA = "SDWA"; 1012 int SDWA_ID = 2; 1013 string SDWA9 = "SDWA9"; 1014 int SDWA9_ID = 3; 1015 string DPP = "DPP"; 1016 int DPP_ID = 4; 1017 string Disable = "Disable"; 1018 int Disable_ID = 5; 1019} 1020 1021def DefaultAMDGPUAsmParserVariant : AsmParserVariant { 1022 let Variant = AMDGPUAsmVariants.Default_ID; 1023 let Name = AMDGPUAsmVariants.Default; 1024} 1025 1026def VOP3AsmParserVariant : AsmParserVariant { 1027 let Variant = AMDGPUAsmVariants.VOP3_ID; 1028 let Name = AMDGPUAsmVariants.VOP3; 1029} 1030 1031def SDWAAsmParserVariant : AsmParserVariant { 1032 let Variant = AMDGPUAsmVariants.SDWA_ID; 1033 let Name = AMDGPUAsmVariants.SDWA; 1034} 1035 1036def SDWA9AsmParserVariant : AsmParserVariant { 1037 let Variant = AMDGPUAsmVariants.SDWA9_ID; 1038 let Name = AMDGPUAsmVariants.SDWA9; 1039} 1040 1041 1042def DPPAsmParserVariant : AsmParserVariant { 1043 let Variant = AMDGPUAsmVariants.DPP_ID; 1044 let Name = AMDGPUAsmVariants.DPP; 1045} 1046 1047def AMDGPU : Target { 1048 // Pull in Instruction Info: 1049 let InstructionSet = AMDGPUInstrInfo; 1050 let AssemblyParsers = [AMDGPUAsmParser]; 1051 let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant, 1052 VOP3AsmParserVariant, 1053 SDWAAsmParserVariant, 1054 SDWA9AsmParserVariant, 1055 DPPAsmParserVariant]; 1056 let AssemblyWriters = [AMDGPUAsmWriter]; 1057 let AllowRegisterRenaming = 1; 1058} 1059 1060// Dummy Instruction itineraries for pseudo instructions 1061def ALU_NULL : FuncUnit; 1062def NullALU : InstrItinClass; 1063 1064//===----------------------------------------------------------------------===// 1065// Predicate helper class 1066//===----------------------------------------------------------------------===// 1067 1068def isGFX6 : 1069 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">, 1070 AssemblerPredicate<(all_of FeatureSouthernIslands)>; 1071 1072def isGFX6GFX7 : 1073 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" 1074 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, 1075 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>; 1076 1077def isGFX6GFX7GFX10 : 1078 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" 1079 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" 1080 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, 1081 AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>; 1082 1083def isGFX7Only : 1084 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, 1085 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>; 1086 1087def isGFX7GFX10 : 1088 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" 1089 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, 1090 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>; 1091 1092def isGFX7GFX8 : 1093 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" 1094 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS">, 1095 AssemblerPredicate<(all_of FeatureSouthernIslands, FeatureCIInsts)>; 1096 1097def isGFX7GFX8GFX9 : 1098 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" 1099 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" 1100 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, 1101 AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>; 1102 1103def isGFX6GFX7GFX8GFX9 : 1104 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" 1105 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" 1106 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" 1107 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, 1108 AssemblerPredicate<(all_of (not FeatureGFX10Insts))>; 1109 1110def isGFX7Plus : 1111 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">, 1112 AssemblerPredicate<(all_of FeatureCIInsts)>; 1113 1114def isGFX8Plus : 1115 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, 1116 AssemblerPredicate<(all_of FeatureGFX8Insts)>; 1117 1118def isGFX8Only : Predicate<"Subtarget->getGeneration() ==" 1119 "AMDGPUSubtarget::VOLCANIC_ISLANDS">, 1120 AssemblerPredicate <(all_of FeatureVolcanicIslands)>; 1121 1122def isGFX9Plus : 1123 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, 1124 AssemblerPredicate<(all_of FeatureGFX9Insts)>; 1125 1126def isGFX9Only : Predicate < 1127 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, 1128 AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>; 1129 1130def isGFX8GFX9 : 1131 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" 1132 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, 1133 AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>; 1134 1135def isGFX10Plus : 1136 Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">, 1137 AssemblerPredicate<(all_of FeatureGFX10Insts)>; 1138 1139def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">, 1140 AssemblerPredicate<(all_of FeatureFlatAddressSpace)>; 1141 1142def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">, 1143 AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>; 1144def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">, 1145 AssemblerPredicate<(all_of FeatureFlatScratchInsts)>; 1146def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">, 1147 AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>; 1148def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">, 1149 AssemblerPredicate<(all_of FeatureGFX9Insts)>; 1150 1151def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">, 1152 AssemblerPredicate<(any_of FeatureGFX10_3Insts)>; 1153 1154def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">, 1155 AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>; 1156 1157def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">, 1158 AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>; 1159def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">, 1160 AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>; 1161 1162def D16PreservesUnusedBits : 1163 Predicate<"Subtarget->d16PreservesUnusedBits()">, 1164 AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>; 1165 1166def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">; 1167def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">; 1168 1169def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, 1170 AssemblerPredicate<(all_of FeatureGFX9Insts)>; 1171 1172def HasLDSFPAtomics : Predicate<"Subtarget->hasLDSFPAtomics()">, 1173 AssemblerPredicate<(all_of FeatureGFX8Insts)>; 1174 1175def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">, 1176 AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>; 1177 1178def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">; 1179 1180def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">, 1181 AssemblerPredicate<(all_of Feature16BitInsts)>; 1182def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">, 1183 AssemblerPredicate<(all_of FeatureVOP3P)>; 1184 1185def HasMinMaxDenormModes : Predicate<"Subtarget->supportsMinMaxDenormModes()">; 1186def NotHasMinMaxDenormModes : Predicate<"!Subtarget->supportsMinMaxDenormModes()">; 1187 1188def HasSDWA : Predicate<"Subtarget->hasSDWA()">, 1189 AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>; 1190 1191def HasSDWA9 : 1192 Predicate<"Subtarget->hasSDWA()">, 1193 AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>; 1194 1195def HasSDWA10 : 1196 Predicate<"Subtarget->hasSDWA()">, 1197 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>; 1198 1199def HasDPP : Predicate<"Subtarget->hasDPP()">, 1200 AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>; 1201 1202def HasDPP8 : Predicate<"Subtarget->hasDPP8()">, 1203 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>; 1204 1205def HasR128A16 : Predicate<"Subtarget->hasR128A16()">, 1206 AssemblerPredicate<(all_of FeatureR128A16)>; 1207 1208def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">, 1209 AssemblerPredicate<(all_of FeatureGFX10A16)>; 1210 1211def HasG16 : Predicate<"Subtarget->hasG16()">, 1212 AssemblerPredicate<(all_of FeatureG16)>; 1213 1214def HasDPP16 : Predicate<"Subtarget->hasDPP()">, 1215 AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>; 1216 1217def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">, 1218 AssemblerPredicate<(all_of FeatureIntClamp)>; 1219 1220def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">, 1221 AssemblerPredicate<(all_of FeatureMadMixInsts)>; 1222 1223def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">, 1224 AssemblerPredicate<(all_of FeatureScalarStores)>; 1225 1226def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">, 1227 AssemblerPredicate<(all_of FeatureScalarAtomics)>; 1228 1229def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">, 1230 AssemblerPredicate<(all_of FeatureNoSdstCMPX)>; 1231 1232def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">, 1233 AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>; 1234 1235def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; 1236def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; 1237def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">, 1238 AssemblerPredicate<(all_of FeatureVGPRIndexMode)>; 1239def HasMovrel : Predicate<"Subtarget->hasMovrel()">, 1240 AssemblerPredicate<(all_of FeatureMovrel)>; 1241 1242def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">, 1243 AssemblerPredicate<(all_of FeatureFmaMixInsts)>; 1244 1245def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">, 1246 AssemblerPredicate<(all_of FeatureDLInsts)>; 1247 1248def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">, 1249 AssemblerPredicate<(all_of FeatureDot1Insts)>; 1250 1251def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">, 1252 AssemblerPredicate<(all_of FeatureDot2Insts)>; 1253 1254def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">, 1255 AssemblerPredicate<(all_of FeatureDot3Insts)>; 1256 1257def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">, 1258 AssemblerPredicate<(all_of FeatureDot4Insts)>; 1259 1260def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">, 1261 AssemblerPredicate<(all_of FeatureDot5Insts)>; 1262 1263def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">, 1264 AssemblerPredicate<(all_of FeatureDot6Insts)>; 1265 1266def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">, 1267 AssemblerPredicate<(all_of FeatureGetWaveIdInst)>; 1268 1269def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">, 1270 AssemblerPredicate<(all_of FeatureMAIInsts)>; 1271 1272def HasSMemTimeInst : Predicate<"Subtarget->hasSMemTimeInst()">, 1273 AssemblerPredicate<(all_of FeatureSMemTimeInst)>; 1274 1275def HasNoSMemTimeInst : Predicate<"!Subtarget->hasSMemTimeInst()">; 1276 1277def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">, 1278 AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>; 1279 1280def HasMadMacF32Insts : Predicate<"Subtarget->hasMadMacF32Insts()">, 1281 AssemblerPredicate<(all_of FeatureMadMacF32Insts)>; 1282 1283def HasFmaLegacy32 : Predicate<"Subtarget->hasGFX10_3Insts()">, 1284 AssemblerPredicate<(any_of FeatureGFX10_3Insts)>; 1285 1286def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">, 1287 AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>; 1288 1289def HasDsSrc2Insts : Predicate<"!Subtarget->hasDsSrc2Insts()">, 1290 AssemblerPredicate<(all_of FeatureDsSrc2Insts)>; 1291 1292def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">, 1293 AssemblerPredicate<(all_of FeatureOffset3fBug)>; 1294 1295def EnableLateCFGStructurize : Predicate< 1296 "EnableLateStructurizeCFG">; 1297 1298def EnableFlatScratch : Predicate<"Subtarget->enableFlatScratch()">; 1299 1300def DisableFlatScratch : Predicate<"!Subtarget->enableFlatScratch()">; 1301 1302// Include AMDGPU TD files 1303include "SISchedule.td" 1304include "GCNProcessors.td" 1305include "AMDGPUInstrInfo.td" 1306include "SIRegisterInfo.td" 1307include "AMDGPURegisterBanks.td" 1308include "AMDGPUInstructions.td" 1309include "SIInstrInfo.td" 1310include "AMDGPUCallingConv.td" 1311include "AMDGPUSearchableTables.td" 1312