1 //=== lib/CodeGen/GlobalISel/AMDGPURegBankCombiner.cpp ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass does combining of machine instructions at the generic MI level,
10 // after register banks are known.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AMDGPUTargetMachine.h"
15 #include "AMDGPULegalizerInfo.h"
16 #include "llvm/CodeGen/GlobalISel/Combiner.h"
17 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
18 #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
19 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/Support/Debug.h"
25 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
26
27 #define DEBUG_TYPE "amdgpu-regbank-combiner"
28
29 using namespace llvm;
30 using namespace MIPatternMatch;
31
32
33 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
34 #include "AMDGPUGenRegBankGICombiner.inc"
35 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_DEPS
36
37 namespace {
38 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
39 #include "AMDGPUGenRegBankGICombiner.inc"
40 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_H
41
42 class AMDGPURegBankCombinerInfo final : public CombinerInfo {
43 GISelKnownBits *KB;
44 MachineDominatorTree *MDT;
45
46 public:
47 AMDGPUGenRegBankCombinerHelperRuleConfig GeneratedRuleCfg;
48
AMDGPURegBankCombinerInfo(bool EnableOpt,bool OptSize,bool MinSize,const AMDGPULegalizerInfo * LI,GISelKnownBits * KB,MachineDominatorTree * MDT)49 AMDGPURegBankCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
50 const AMDGPULegalizerInfo *LI,
51 GISelKnownBits *KB, MachineDominatorTree *MDT)
52 : CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
53 /*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
54 KB(KB), MDT(MDT) {
55 if (!GeneratedRuleCfg.parseCommandLineOption())
56 report_fatal_error("Invalid rule identifier");
57 }
58
59 bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
60 MachineIRBuilder &B) const override;
61 };
62
combine(GISelChangeObserver & Observer,MachineInstr & MI,MachineIRBuilder & B) const63 bool AMDGPURegBankCombinerInfo::combine(GISelChangeObserver &Observer,
64 MachineInstr &MI,
65 MachineIRBuilder &B) const {
66 CombinerHelper Helper(Observer, B, KB, MDT);
67 AMDGPUGenRegBankCombinerHelper Generated(GeneratedRuleCfg);
68
69 if (Generated.tryCombineAll(Observer, MI, B, Helper))
70 return true;
71
72 return false;
73 }
74
75 #define AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
76 #include "AMDGPUGenRegBankGICombiner.inc"
77 #undef AMDGPUREGBANKCOMBINERHELPER_GENCOMBINERHELPER_CPP
78
79 // Pass boilerplate
80 // ================
81
82 class AMDGPURegBankCombiner : public MachineFunctionPass {
83 public:
84 static char ID;
85
86 AMDGPURegBankCombiner(bool IsOptNone = false);
87
getPassName() const88 StringRef getPassName() const override {
89 return "AMDGPURegBankCombiner";
90 }
91
92 bool runOnMachineFunction(MachineFunction &MF) override;
93
94 void getAnalysisUsage(AnalysisUsage &AU) const override;
95 private:
96 bool IsOptNone;
97 };
98 } // end anonymous namespace
99
getAnalysisUsage(AnalysisUsage & AU) const100 void AMDGPURegBankCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
101 AU.addRequired<TargetPassConfig>();
102 AU.setPreservesCFG();
103 getSelectionDAGFallbackAnalysisUsage(AU);
104 AU.addRequired<GISelKnownBitsAnalysis>();
105 AU.addPreserved<GISelKnownBitsAnalysis>();
106 if (!IsOptNone) {
107 AU.addRequired<MachineDominatorTree>();
108 AU.addPreserved<MachineDominatorTree>();
109 }
110 MachineFunctionPass::getAnalysisUsage(AU);
111 }
112
AMDGPURegBankCombiner(bool IsOptNone)113 AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
114 : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
115 initializeAMDGPURegBankCombinerPass(*PassRegistry::getPassRegistry());
116 }
117
runOnMachineFunction(MachineFunction & MF)118 bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
119 if (MF.getProperties().hasProperty(
120 MachineFunctionProperties::Property::FailedISel))
121 return false;
122 auto *TPC = &getAnalysis<TargetPassConfig>();
123 const Function &F = MF.getFunction();
124 bool EnableOpt =
125 MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
126
127 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
128 const AMDGPULegalizerInfo *LI
129 = static_cast<const AMDGPULegalizerInfo *>(ST.getLegalizerInfo());
130
131 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
132 MachineDominatorTree *MDT =
133 IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
134 AMDGPURegBankCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
135 F.hasMinSize(), LI, KB, MDT);
136 Combiner C(PCInfo, TPC);
137 return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
138 }
139
140 char AMDGPURegBankCombiner::ID = 0;
141 INITIALIZE_PASS_BEGIN(AMDGPURegBankCombiner, DEBUG_TYPE,
142 "Combine AMDGPU machine instrs after regbankselect",
143 false, false)
144 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
145 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
146 INITIALIZE_PASS_END(AMDGPURegBankCombiner, DEBUG_TYPE,
147 "Combine AMDGPU machine instrs after regbankselect", false,
148 false)
149
150 namespace llvm {
createAMDGPURegBankCombiner(bool IsOptNone)151 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone) {
152 return new AMDGPURegBankCombiner(IsOptNone);
153 }
154 } // end namespace llvm
155