1//=-HexagonScheduleV5.td - HexagonV5 Scheduling Definitions --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9def LD_tc_ld_SLOT01 : InstrItinClass;
10def ST_tc_st_SLOT01 : InstrItinClass;
11
12class HexagonV5PseudoItin {
13  list<InstrItinData> V5PseudoItin_list = [
14    InstrItinData<PSEUDO,     [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
15    InstrItinData<PSEUDOM,    [InstrStage<1, [SLOT2, SLOT3], 0>,
16                               InstrStage<1, [SLOT2, SLOT3]>]>,
17    InstrItinData<DUPLEX,     [InstrStage<1, [SLOT0]>]>,
18    InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
19  ];
20}
21
22def HexagonV5ItinList : DepScalarItinV5, HexagonV5PseudoItin {
23  list<InstrItinData> V5Itin_list = [
24    InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
25    InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
26  ];
27  list<InstrItinData> ItinList =
28    !listconcat(V5Itin_list, DepScalarItinV5_list, V5PseudoItin_list);
29}
30
31def HexagonItinerariesV5 :
32      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
33                           [Hex_FWD], HexagonV5ItinList.ItinList>;
34
35def HexagonModelV5 : SchedMachineModel {
36  // Max issue per cycle == bundle width.
37  let IssueWidth = 4;
38  let Itineraries = HexagonItinerariesV5;
39  let LoadLatency = 1;
40  let CompleteModel = 0;
41}
42
43//===----------------------------------------------------------------------===//
44// Hexagon V5 Resource Definitions -
45//===----------------------------------------------------------------------===//
46