1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an PPC MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/PPCInstPrinter.h"
14 #include "MCTargetDesc/PPCMCTargetDesc.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCInstrInfo.h"
17 #include "llvm/CodeGen/TargetOpcodes.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
26 using namespace llvm;
27
28 #define DEBUG_TYPE "asm-printer"
29
30 // FIXME: Once the integrated assembler supports full register names, tie this
31 // to the verbose-asm setting.
32 static cl::opt<bool>
33 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34 cl::desc("Use full register names when printing assembly"));
35
36 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
37 static cl::opt<bool>
38 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
39 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
40
41 // Prints full register names with percent symbol.
42 static cl::opt<bool>
43 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
44 cl::init(false),
45 cl::desc("Prints full register names with percent"));
46
47 #define PRINT_ALIAS_INSTR
48 #include "PPCGenAsmWriter.inc"
49
printRegName(raw_ostream & OS,unsigned RegNo) const50 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 const char *RegName = getRegisterName(RegNo);
52 OS << RegName;
53 }
54
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)55 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
56 StringRef Annot, const MCSubtargetInfo &STI,
57 raw_ostream &O) {
58 // Customize printing of the addis instruction on AIX. When an operand is a
59 // symbol reference, the instruction syntax is changed to look like a load
60 // operation, i.e:
61 // Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
62 if (TT.isOSAIX() &&
63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
64 MI->getOperand(2).isExpr()) {
65 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
66 "The first and the second operand of an addis instruction"
67 " should be registers.");
68
69 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
70 "The third operand of an addis instruction should be a symbol "
71 "reference expression if it is an expression at all.");
72
73 O << "\taddis ";
74 printOperand(MI, 0, O);
75 O << ", ";
76 printOperand(MI, 2, O);
77 O << "(";
78 printOperand(MI, 1, O);
79 O << ")";
80 return;
81 }
82
83 // Check if the last operand is an expression with the variant kind
84 // VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
85 // relocation and the .reloc directive needs to be added.
86 unsigned LastOp = MI->getNumOperands() - 1;
87 if (MI->getNumOperands() > 1) {
88 const MCOperand &Operand = MI->getOperand(LastOp);
89 if (Operand.isExpr()) {
90 const MCExpr *Expr = Operand.getExpr();
91 const MCSymbolRefExpr *SymExpr =
92 static_cast<const MCSymbolRefExpr *>(Expr);
93
94 if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
95 const MCSymbol &Symbol = SymExpr->getSymbol();
96 if (MI->getOpcode() == PPC::PLDpc) {
97 printInstruction(MI, Address, O);
98 O << "\n";
99 Symbol.print(O, &MAI);
100 O << ":";
101 return;
102 } else {
103 O << "\t.reloc ";
104 Symbol.print(O, &MAI);
105 O << "-8,R_PPC64_PCREL_OPT,.-(";
106 Symbol.print(O, &MAI);
107 O << "-8)\n";
108 }
109 }
110 }
111 }
112
113 // Check for slwi/srwi mnemonics.
114 if (MI->getOpcode() == PPC::RLWINM) {
115 unsigned char SH = MI->getOperand(2).getImm();
116 unsigned char MB = MI->getOperand(3).getImm();
117 unsigned char ME = MI->getOperand(4).getImm();
118 bool useSubstituteMnemonic = false;
119 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
120 O << "\tslwi "; useSubstituteMnemonic = true;
121 }
122 if (SH <= 31 && MB == (32-SH) && ME == 31) {
123 O << "\tsrwi "; useSubstituteMnemonic = true;
124 SH = 32-SH;
125 }
126 if (useSubstituteMnemonic) {
127 printOperand(MI, 0, O);
128 O << ", ";
129 printOperand(MI, 1, O);
130 O << ", " << (unsigned int)SH;
131
132 printAnnotation(O, Annot);
133 return;
134 }
135 }
136
137 if (MI->getOpcode() == PPC::RLDICR ||
138 MI->getOpcode() == PPC::RLDICR_32) {
139 unsigned char SH = MI->getOperand(2).getImm();
140 unsigned char ME = MI->getOperand(3).getImm();
141 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
142 if (63-SH == ME) {
143 O << "\tsldi ";
144 printOperand(MI, 0, O);
145 O << ", ";
146 printOperand(MI, 1, O);
147 O << ", " << (unsigned int)SH;
148 printAnnotation(O, Annot);
149 return;
150 }
151 }
152
153 // dcbt[st] is printed manually here because:
154 // 1. The assembly syntax is different between embedded and server targets
155 // 2. We must print the short mnemonics for TH == 0 because the
156 // embedded/server syntax default will not be stable across assemblers
157 // The syntax for dcbt is:
158 // dcbt ra, rb, th [server]
159 // dcbt th, ra, rb [embedded]
160 // where th can be omitted when it is 0. dcbtst is the same.
161 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
162 unsigned char TH = MI->getOperand(0).getImm();
163 O << "\tdcbt";
164 if (MI->getOpcode() == PPC::DCBTST)
165 O << "st";
166 if (TH == 16)
167 O << "t";
168 O << " ";
169
170 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
171 if (IsBookE && TH != 0 && TH != 16)
172 O << (unsigned int) TH << ", ";
173
174 printOperand(MI, 1, O);
175 O << ", ";
176 printOperand(MI, 2, O);
177
178 if (!IsBookE && TH != 0 && TH != 16)
179 O << ", " << (unsigned int) TH;
180
181 printAnnotation(O, Annot);
182 return;
183 }
184
185 if (MI->getOpcode() == PPC::DCBF) {
186 unsigned char L = MI->getOperand(0).getImm();
187 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
188 O << "\tdcb";
189 if (L != 6)
190 O << "f";
191 if (L == 1)
192 O << "l";
193 if (L == 3)
194 O << "lp";
195 if (L == 4)
196 O << "ps";
197 if (L == 6)
198 O << "stps";
199 O << " ";
200
201 printOperand(MI, 1, O);
202 O << ", ";
203 printOperand(MI, 2, O);
204
205 printAnnotation(O, Annot);
206 return;
207 }
208 }
209
210 if (!printAliasInstr(MI, Address, O))
211 printInstruction(MI, Address, O);
212 printAnnotation(O, Annot);
213 }
214
printPredicateOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O,const char * Modifier)215 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
216 raw_ostream &O,
217 const char *Modifier) {
218 unsigned Code = MI->getOperand(OpNo).getImm();
219
220 if (StringRef(Modifier) == "cc") {
221 switch ((PPC::Predicate)Code) {
222 case PPC::PRED_LT_MINUS:
223 case PPC::PRED_LT_PLUS:
224 case PPC::PRED_LT:
225 O << "lt";
226 return;
227 case PPC::PRED_LE_MINUS:
228 case PPC::PRED_LE_PLUS:
229 case PPC::PRED_LE:
230 O << "le";
231 return;
232 case PPC::PRED_EQ_MINUS:
233 case PPC::PRED_EQ_PLUS:
234 case PPC::PRED_EQ:
235 O << "eq";
236 return;
237 case PPC::PRED_GE_MINUS:
238 case PPC::PRED_GE_PLUS:
239 case PPC::PRED_GE:
240 O << "ge";
241 return;
242 case PPC::PRED_GT_MINUS:
243 case PPC::PRED_GT_PLUS:
244 case PPC::PRED_GT:
245 O << "gt";
246 return;
247 case PPC::PRED_NE_MINUS:
248 case PPC::PRED_NE_PLUS:
249 case PPC::PRED_NE:
250 O << "ne";
251 return;
252 case PPC::PRED_UN_MINUS:
253 case PPC::PRED_UN_PLUS:
254 case PPC::PRED_UN:
255 O << "un";
256 return;
257 case PPC::PRED_NU_MINUS:
258 case PPC::PRED_NU_PLUS:
259 case PPC::PRED_NU:
260 O << "nu";
261 return;
262 case PPC::PRED_BIT_SET:
263 case PPC::PRED_BIT_UNSET:
264 llvm_unreachable("Invalid use of bit predicate code");
265 }
266 llvm_unreachable("Invalid predicate code");
267 }
268
269 if (StringRef(Modifier) == "pm") {
270 switch ((PPC::Predicate)Code) {
271 case PPC::PRED_LT:
272 case PPC::PRED_LE:
273 case PPC::PRED_EQ:
274 case PPC::PRED_GE:
275 case PPC::PRED_GT:
276 case PPC::PRED_NE:
277 case PPC::PRED_UN:
278 case PPC::PRED_NU:
279 return;
280 case PPC::PRED_LT_MINUS:
281 case PPC::PRED_LE_MINUS:
282 case PPC::PRED_EQ_MINUS:
283 case PPC::PRED_GE_MINUS:
284 case PPC::PRED_GT_MINUS:
285 case PPC::PRED_NE_MINUS:
286 case PPC::PRED_UN_MINUS:
287 case PPC::PRED_NU_MINUS:
288 O << "-";
289 return;
290 case PPC::PRED_LT_PLUS:
291 case PPC::PRED_LE_PLUS:
292 case PPC::PRED_EQ_PLUS:
293 case PPC::PRED_GE_PLUS:
294 case PPC::PRED_GT_PLUS:
295 case PPC::PRED_NE_PLUS:
296 case PPC::PRED_UN_PLUS:
297 case PPC::PRED_NU_PLUS:
298 O << "+";
299 return;
300 case PPC::PRED_BIT_SET:
301 case PPC::PRED_BIT_UNSET:
302 llvm_unreachable("Invalid use of bit predicate code");
303 }
304 llvm_unreachable("Invalid predicate code");
305 }
306
307 assert(StringRef(Modifier) == "reg" &&
308 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
309 printOperand(MI, OpNo+1, O);
310 }
311
printATBitsAsHint(const MCInst * MI,unsigned OpNo,raw_ostream & O)312 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
313 raw_ostream &O) {
314 unsigned Code = MI->getOperand(OpNo).getImm();
315 if (Code == 2)
316 O << "-";
317 else if (Code == 3)
318 O << "+";
319 }
320
printU1ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)321 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
322 raw_ostream &O) {
323 unsigned int Value = MI->getOperand(OpNo).getImm();
324 assert(Value <= 1 && "Invalid u1imm argument!");
325 O << (unsigned int)Value;
326 }
327
printU2ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)328 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
329 raw_ostream &O) {
330 unsigned int Value = MI->getOperand(OpNo).getImm();
331 assert(Value <= 3 && "Invalid u2imm argument!");
332 O << (unsigned int)Value;
333 }
334
printU3ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)335 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
336 raw_ostream &O) {
337 unsigned int Value = MI->getOperand(OpNo).getImm();
338 assert(Value <= 8 && "Invalid u3imm argument!");
339 O << (unsigned int)Value;
340 }
341
printU4ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)342 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
343 raw_ostream &O) {
344 unsigned int Value = MI->getOperand(OpNo).getImm();
345 assert(Value <= 15 && "Invalid u4imm argument!");
346 O << (unsigned int)Value;
347 }
348
printS5ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)349 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
350 raw_ostream &O) {
351 int Value = MI->getOperand(OpNo).getImm();
352 Value = SignExtend32<5>(Value);
353 O << (int)Value;
354 }
355
printImmZeroOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)356 void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
357 raw_ostream &O) {
358 unsigned int Value = MI->getOperand(OpNo).getImm();
359 assert(Value == 0 && "Operand must be zero");
360 O << (unsigned int)Value;
361 }
362
printU5ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)363 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
364 raw_ostream &O) {
365 unsigned int Value = MI->getOperand(OpNo).getImm();
366 assert(Value <= 31 && "Invalid u5imm argument!");
367 O << (unsigned int)Value;
368 }
369
printU6ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)370 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
371 raw_ostream &O) {
372 unsigned int Value = MI->getOperand(OpNo).getImm();
373 assert(Value <= 63 && "Invalid u6imm argument!");
374 O << (unsigned int)Value;
375 }
376
printU7ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)377 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
378 raw_ostream &O) {
379 unsigned int Value = MI->getOperand(OpNo).getImm();
380 assert(Value <= 127 && "Invalid u7imm argument!");
381 O << (unsigned int)Value;
382 }
383
384 // Operands of BUILD_VECTOR are signed and we use this to print operands
385 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
386 // print as unsigned.
printU8ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)387 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
388 raw_ostream &O) {
389 unsigned char Value = MI->getOperand(OpNo).getImm();
390 O << (unsigned int)Value;
391 }
392
printU10ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)393 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
394 raw_ostream &O) {
395 unsigned short Value = MI->getOperand(OpNo).getImm();
396 assert(Value <= 1023 && "Invalid u10imm argument!");
397 O << (unsigned short)Value;
398 }
399
printU12ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)400 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
401 raw_ostream &O) {
402 unsigned short Value = MI->getOperand(OpNo).getImm();
403 assert(Value <= 4095 && "Invalid u12imm argument!");
404 O << (unsigned short)Value;
405 }
406
printS16ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)407 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
408 raw_ostream &O) {
409 if (MI->getOperand(OpNo).isImm())
410 O << (short)MI->getOperand(OpNo).getImm();
411 else
412 printOperand(MI, OpNo, O);
413 }
414
printS34ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)415 void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
416 raw_ostream &O) {
417 if (MI->getOperand(OpNo).isImm()) {
418 long long Value = MI->getOperand(OpNo).getImm();
419 assert(isInt<34>(Value) && "Invalid s34imm argument!");
420 O << (long long)Value;
421 }
422 else
423 printOperand(MI, OpNo, O);
424 }
425
printU16ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)426 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
427 raw_ostream &O) {
428 if (MI->getOperand(OpNo).isImm())
429 O << (unsigned short)MI->getOperand(OpNo).getImm();
430 else
431 printOperand(MI, OpNo, O);
432 }
433
printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,raw_ostream & O)434 void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
435 unsigned OpNo, raw_ostream &O) {
436 if (!MI->getOperand(OpNo).isImm())
437 return printOperand(MI, OpNo, O);
438 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
439 if (PrintBranchImmAsAddress) {
440 uint64_t Target = Address + Imm;
441 if (!TT.isPPC64())
442 Target &= 0xffffffff;
443 O << formatHex(Target);
444 } else {
445 // Branches can take an immediate operand. This is used by the branch
446 // selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
447 // to express an eight byte displacement from the program counter.
448 if (!TT.isOSAIX())
449 O << ".";
450 else
451 O << "$";
452
453 if (Imm >= 0)
454 O << "+";
455 O << Imm;
456 }
457 }
458
printAbsBranchOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)459 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
460 raw_ostream &O) {
461 if (!MI->getOperand(OpNo).isImm())
462 return printOperand(MI, OpNo, O);
463
464 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
465 }
466
467
printcrbitm(const MCInst * MI,unsigned OpNo,raw_ostream & O)468 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
469 raw_ostream &O) {
470 unsigned CCReg = MI->getOperand(OpNo).getReg();
471 unsigned RegNo;
472 switch (CCReg) {
473 default: llvm_unreachable("Unknown CR register");
474 case PPC::CR0: RegNo = 0; break;
475 case PPC::CR1: RegNo = 1; break;
476 case PPC::CR2: RegNo = 2; break;
477 case PPC::CR3: RegNo = 3; break;
478 case PPC::CR4: RegNo = 4; break;
479 case PPC::CR5: RegNo = 5; break;
480 case PPC::CR6: RegNo = 6; break;
481 case PPC::CR7: RegNo = 7; break;
482 }
483 O << (0x80 >> RegNo);
484 }
485
printMemRegImm(const MCInst * MI,unsigned OpNo,raw_ostream & O)486 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
487 raw_ostream &O) {
488 printS16ImmOperand(MI, OpNo, O);
489 O << '(';
490 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
491 O << "0";
492 else
493 printOperand(MI, OpNo+1, O);
494 O << ')';
495 }
496
printMemRegImm34PCRel(const MCInst * MI,unsigned OpNo,raw_ostream & O)497 void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
498 raw_ostream &O) {
499 printS34ImmOperand(MI, OpNo, O);
500 O << '(';
501 printImmZeroOperand(MI, OpNo + 1, O);
502 O << ')';
503 }
504
printMemRegImm34(const MCInst * MI,unsigned OpNo,raw_ostream & O)505 void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
506 raw_ostream &O) {
507 printS34ImmOperand(MI, OpNo, O);
508 O << '(';
509 printOperand(MI, OpNo + 1, O);
510 O << ')';
511 }
512
printMemRegReg(const MCInst * MI,unsigned OpNo,raw_ostream & O)513 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
514 raw_ostream &O) {
515 // When used as the base register, r0 reads constant zero rather than
516 // the value contained in the register. For this reason, the darwin
517 // assembler requires that we print r0 as 0 (no r) when used as the base.
518 if (MI->getOperand(OpNo).getReg() == PPC::R0)
519 O << "0";
520 else
521 printOperand(MI, OpNo, O);
522 O << ", ";
523 printOperand(MI, OpNo+1, O);
524 }
525
printTLSCall(const MCInst * MI,unsigned OpNo,raw_ostream & O)526 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
527 raw_ostream &O) {
528 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
529 // come at the _end_ of the expression.
530 const MCOperand &Op = MI->getOperand(OpNo);
531 const MCSymbolRefExpr *RefExp = nullptr;
532 const MCConstantExpr *ConstExp = nullptr;
533 if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
534 RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
535 ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
536 } else
537 RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
538
539 O << RefExp->getSymbol().getName();
540 // The variant kind VK_PPC_NOTOC needs to be handled as a special case
541 // because we do not want the assembly to print out the @notoc at the
542 // end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
543 // like __tls_get_addr@notoc(x@tlsgd).
544 if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
545 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
546 O << '(';
547 printOperand(MI, OpNo+1, O);
548 O << ')';
549 if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
550 RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC)
551 O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
552 if (ConstExp != nullptr)
553 O << '+' << ConstExp->getValue();
554 }
555
556 /// showRegistersWithPercentPrefix - Check if this register name should be
557 /// printed with a percentage symbol as prefix.
showRegistersWithPercentPrefix(const char * RegName) const558 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
559 if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
560 return false;
561
562 switch (RegName[0]) {
563 default:
564 return false;
565 case 'r':
566 case 'f':
567 case 'q':
568 case 'v':
569 case 'c':
570 return true;
571 }
572 }
573
574 /// getVerboseConditionalRegName - This method expands the condition register
575 /// when requested explicitly or targetting Darwin.
getVerboseConditionRegName(unsigned RegNum,unsigned RegEncoding) const576 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
577 unsigned RegEncoding)
578 const {
579 if (!TT.isOSDarwin() && !FullRegNames)
580 return nullptr;
581 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
582 return nullptr;
583 const char *CRBits[] = {
584 "lt", "gt", "eq", "un",
585 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
586 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
587 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
588 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
589 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
590 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
591 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
592 };
593 return CRBits[RegEncoding];
594 }
595
596 // showRegistersWithPrefix - This method determines whether registers
597 // should be number-only or include the prefix.
showRegistersWithPrefix() const598 bool PPCInstPrinter::showRegistersWithPrefix() const {
599 if (TT.getOS() == Triple::AIX)
600 return false;
601 return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
602 }
603
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)604 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
605 raw_ostream &O) {
606 const MCOperand &Op = MI->getOperand(OpNo);
607 if (Op.isReg()) {
608 unsigned Reg = Op.getReg();
609 if (!ShowVSRNumsAsVR)
610 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
611 Reg, OpNo);
612
613 const char *RegName;
614 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
615 if (RegName == nullptr)
616 RegName = getRegisterName(Reg);
617 if (showRegistersWithPercentPrefix(RegName))
618 O << "%";
619 if (!showRegistersWithPrefix())
620 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
621
622 O << RegName;
623 return;
624 }
625
626 if (Op.isImm()) {
627 O << Op.getImm();
628 return;
629 }
630
631 assert(Op.isExpr() && "unknown operand kind in printOperand");
632 Op.getExpr()->print(O, &MAI);
633 }
634
635