1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "TargetInfo/SystemZTargetInfo.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCAsmParser.h"
21 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/SMLoc.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <iterator>
35 #include <memory>
36 #include <string>
37
38 using namespace llvm;
39
40 // Return true if Expr is in the range [MinValue, MaxValue].
inRange(const MCExpr * Expr,int64_t MinValue,int64_t MaxValue)41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43 int64_t Value = CE->getValue();
44 return Value >= MinValue && Value <= MaxValue;
45 }
46 return false;
47 }
48
49 namespace {
50
51 enum RegisterKind {
52 GR32Reg,
53 GRH32Reg,
54 GR64Reg,
55 GR128Reg,
56 FP32Reg,
57 FP64Reg,
58 FP128Reg,
59 VR32Reg,
60 VR64Reg,
61 VR128Reg,
62 AR32Reg,
63 CR64Reg,
64 };
65
66 enum MemoryKind {
67 BDMem,
68 BDXMem,
69 BDLMem,
70 BDRMem,
71 BDVMem
72 };
73
74 class SystemZOperand : public MCParsedAsmOperand {
75 private:
76 enum OperandKind {
77 KindInvalid,
78 KindToken,
79 KindReg,
80 KindImm,
81 KindImmTLS,
82 KindMem
83 };
84
85 OperandKind Kind;
86 SMLoc StartLoc, EndLoc;
87
88 // A string of length Length, starting at Data.
89 struct TokenOp {
90 const char *Data;
91 unsigned Length;
92 };
93
94 // LLVM register Num, which has kind Kind. In some ways it might be
95 // easier for this class to have a register bank (general, floating-point
96 // or access) and a raw register number (0-15). This would postpone the
97 // interpretation of the operand to the add*() methods and avoid the need
98 // for context-dependent parsing. However, we do things the current way
99 // because of the virtual getReg() method, which needs to distinguish
100 // between (say) %r0 used as a single register and %r0 used as a pair.
101 // Context-dependent parsing can also give us slightly better error
102 // messages when invalid pairs like %r1 are used.
103 struct RegOp {
104 RegisterKind Kind;
105 unsigned Num;
106 };
107
108 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
109 // MemKind says what type of memory this is and RegKind says what type
110 // the base register has (GR32Reg or GR64Reg). Length is the operand
111 // length for D(L,B)-style operands, otherwise it is null.
112 struct MemOp {
113 unsigned Base : 12;
114 unsigned Index : 12;
115 unsigned MemKind : 4;
116 unsigned RegKind : 4;
117 const MCExpr *Disp;
118 union {
119 const MCExpr *Imm;
120 unsigned Reg;
121 } Length;
122 };
123
124 // Imm is an immediate operand, and Sym is an optional TLS symbol
125 // for use with a __tls_get_offset marker relocation.
126 struct ImmTLSOp {
127 const MCExpr *Imm;
128 const MCExpr *Sym;
129 };
130
131 union {
132 TokenOp Token;
133 RegOp Reg;
134 const MCExpr *Imm;
135 ImmTLSOp ImmTLS;
136 MemOp Mem;
137 };
138
addExpr(MCInst & Inst,const MCExpr * Expr) const139 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
140 // Add as immediates when possible. Null MCExpr = 0.
141 if (!Expr)
142 Inst.addOperand(MCOperand::createImm(0));
143 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
144 Inst.addOperand(MCOperand::createImm(CE->getValue()));
145 else
146 Inst.addOperand(MCOperand::createExpr(Expr));
147 }
148
149 public:
SystemZOperand(OperandKind kind,SMLoc startLoc,SMLoc endLoc)150 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
151 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
152
153 // Create particular kinds of operand.
createInvalid(SMLoc StartLoc,SMLoc EndLoc)154 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
155 SMLoc EndLoc) {
156 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
157 }
158
createToken(StringRef Str,SMLoc Loc)159 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
160 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
161 Op->Token.Data = Str.data();
162 Op->Token.Length = Str.size();
163 return Op;
164 }
165
166 static std::unique_ptr<SystemZOperand>
createReg(RegisterKind Kind,unsigned Num,SMLoc StartLoc,SMLoc EndLoc)167 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
168 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
169 Op->Reg.Kind = Kind;
170 Op->Reg.Num = Num;
171 return Op;
172 }
173
174 static std::unique_ptr<SystemZOperand>
createImm(const MCExpr * Expr,SMLoc StartLoc,SMLoc EndLoc)175 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
176 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
177 Op->Imm = Expr;
178 return Op;
179 }
180
181 static std::unique_ptr<SystemZOperand>
createMem(MemoryKind MemKind,RegisterKind RegKind,unsigned Base,const MCExpr * Disp,unsigned Index,const MCExpr * LengthImm,unsigned LengthReg,SMLoc StartLoc,SMLoc EndLoc)182 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
183 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
184 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
185 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
186 Op->Mem.MemKind = MemKind;
187 Op->Mem.RegKind = RegKind;
188 Op->Mem.Base = Base;
189 Op->Mem.Index = Index;
190 Op->Mem.Disp = Disp;
191 if (MemKind == BDLMem)
192 Op->Mem.Length.Imm = LengthImm;
193 if (MemKind == BDRMem)
194 Op->Mem.Length.Reg = LengthReg;
195 return Op;
196 }
197
198 static std::unique_ptr<SystemZOperand>
createImmTLS(const MCExpr * Imm,const MCExpr * Sym,SMLoc StartLoc,SMLoc EndLoc)199 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
200 SMLoc StartLoc, SMLoc EndLoc) {
201 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
202 Op->ImmTLS.Imm = Imm;
203 Op->ImmTLS.Sym = Sym;
204 return Op;
205 }
206
207 // Token operands
isToken() const208 bool isToken() const override {
209 return Kind == KindToken;
210 }
getToken() const211 StringRef getToken() const {
212 assert(Kind == KindToken && "Not a token");
213 return StringRef(Token.Data, Token.Length);
214 }
215
216 // Register operands.
isReg() const217 bool isReg() const override {
218 return Kind == KindReg;
219 }
isReg(RegisterKind RegKind) const220 bool isReg(RegisterKind RegKind) const {
221 return Kind == KindReg && Reg.Kind == RegKind;
222 }
getReg() const223 unsigned getReg() const override {
224 assert(Kind == KindReg && "Not a register");
225 return Reg.Num;
226 }
227
228 // Immediate operands.
isImm() const229 bool isImm() const override {
230 return Kind == KindImm;
231 }
isImm(int64_t MinValue,int64_t MaxValue) const232 bool isImm(int64_t MinValue, int64_t MaxValue) const {
233 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
234 }
getImm() const235 const MCExpr *getImm() const {
236 assert(Kind == KindImm && "Not an immediate");
237 return Imm;
238 }
239
240 // Immediate operands with optional TLS symbol.
isImmTLS() const241 bool isImmTLS() const {
242 return Kind == KindImmTLS;
243 }
244
getImmTLS() const245 const ImmTLSOp getImmTLS() const {
246 assert(Kind == KindImmTLS && "Not a TLS immediate");
247 return ImmTLS;
248 }
249
250 // Memory operands.
isMem() const251 bool isMem() const override {
252 return Kind == KindMem;
253 }
isMem(MemoryKind MemKind) const254 bool isMem(MemoryKind MemKind) const {
255 return (Kind == KindMem &&
256 (Mem.MemKind == MemKind ||
257 // A BDMem can be treated as a BDXMem in which the index
258 // register field is 0.
259 (Mem.MemKind == BDMem && MemKind == BDXMem)));
260 }
isMem(MemoryKind MemKind,RegisterKind RegKind) const261 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
262 return isMem(MemKind) && Mem.RegKind == RegKind;
263 }
isMemDisp12(MemoryKind MemKind,RegisterKind RegKind) const264 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
265 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
266 }
isMemDisp20(MemoryKind MemKind,RegisterKind RegKind) const267 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
268 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
269 }
isMemDisp12Len4(RegisterKind RegKind) const270 bool isMemDisp12Len4(RegisterKind RegKind) const {
271 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
272 }
isMemDisp12Len8(RegisterKind RegKind) const273 bool isMemDisp12Len8(RegisterKind RegKind) const {
274 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
275 }
276
getMem() const277 const MemOp& getMem() const {
278 assert(Kind == KindMem && "Not a Mem operand");
279 return Mem;
280 }
281
282 // Override MCParsedAsmOperand.
getStartLoc() const283 SMLoc getStartLoc() const override { return StartLoc; }
getEndLoc() const284 SMLoc getEndLoc() const override { return EndLoc; }
285 void print(raw_ostream &OS) const override;
286
287 /// getLocRange - Get the range between the first and last token of this
288 /// operand.
getLocRange() const289 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
290
291 // Used by the TableGen code to add particular types of operand
292 // to an instruction.
addRegOperands(MCInst & Inst,unsigned N) const293 void addRegOperands(MCInst &Inst, unsigned N) const {
294 assert(N == 1 && "Invalid number of operands");
295 Inst.addOperand(MCOperand::createReg(getReg()));
296 }
addImmOperands(MCInst & Inst,unsigned N) const297 void addImmOperands(MCInst &Inst, unsigned N) const {
298 assert(N == 1 && "Invalid number of operands");
299 addExpr(Inst, getImm());
300 }
addBDAddrOperands(MCInst & Inst,unsigned N) const301 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
302 assert(N == 2 && "Invalid number of operands");
303 assert(isMem(BDMem) && "Invalid operand type");
304 Inst.addOperand(MCOperand::createReg(Mem.Base));
305 addExpr(Inst, Mem.Disp);
306 }
addBDXAddrOperands(MCInst & Inst,unsigned N) const307 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
308 assert(N == 3 && "Invalid number of operands");
309 assert(isMem(BDXMem) && "Invalid operand type");
310 Inst.addOperand(MCOperand::createReg(Mem.Base));
311 addExpr(Inst, Mem.Disp);
312 Inst.addOperand(MCOperand::createReg(Mem.Index));
313 }
addBDLAddrOperands(MCInst & Inst,unsigned N) const314 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
315 assert(N == 3 && "Invalid number of operands");
316 assert(isMem(BDLMem) && "Invalid operand type");
317 Inst.addOperand(MCOperand::createReg(Mem.Base));
318 addExpr(Inst, Mem.Disp);
319 addExpr(Inst, Mem.Length.Imm);
320 }
addBDRAddrOperands(MCInst & Inst,unsigned N) const321 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
322 assert(N == 3 && "Invalid number of operands");
323 assert(isMem(BDRMem) && "Invalid operand type");
324 Inst.addOperand(MCOperand::createReg(Mem.Base));
325 addExpr(Inst, Mem.Disp);
326 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
327 }
addBDVAddrOperands(MCInst & Inst,unsigned N) const328 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
329 assert(N == 3 && "Invalid number of operands");
330 assert(isMem(BDVMem) && "Invalid operand type");
331 Inst.addOperand(MCOperand::createReg(Mem.Base));
332 addExpr(Inst, Mem.Disp);
333 Inst.addOperand(MCOperand::createReg(Mem.Index));
334 }
addImmTLSOperands(MCInst & Inst,unsigned N) const335 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
336 assert(N == 2 && "Invalid number of operands");
337 assert(Kind == KindImmTLS && "Invalid operand type");
338 addExpr(Inst, ImmTLS.Imm);
339 if (ImmTLS.Sym)
340 addExpr(Inst, ImmTLS.Sym);
341 }
342
343 // Used by the TableGen code to check for particular operand types.
isGR32() const344 bool isGR32() const { return isReg(GR32Reg); }
isGRH32() const345 bool isGRH32() const { return isReg(GRH32Reg); }
isGRX32() const346 bool isGRX32() const { return false; }
isGR64() const347 bool isGR64() const { return isReg(GR64Reg); }
isGR128() const348 bool isGR128() const { return isReg(GR128Reg); }
isADDR32() const349 bool isADDR32() const { return isReg(GR32Reg); }
isADDR64() const350 bool isADDR64() const { return isReg(GR64Reg); }
isADDR128() const351 bool isADDR128() const { return false; }
isFP32() const352 bool isFP32() const { return isReg(FP32Reg); }
isFP64() const353 bool isFP64() const { return isReg(FP64Reg); }
isFP128() const354 bool isFP128() const { return isReg(FP128Reg); }
isVR32() const355 bool isVR32() const { return isReg(VR32Reg); }
isVR64() const356 bool isVR64() const { return isReg(VR64Reg); }
isVF128() const357 bool isVF128() const { return false; }
isVR128() const358 bool isVR128() const { return isReg(VR128Reg); }
isAR32() const359 bool isAR32() const { return isReg(AR32Reg); }
isCR64() const360 bool isCR64() const { return isReg(CR64Reg); }
isAnyReg() const361 bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
isBDAddr32Disp12() const362 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
isBDAddr32Disp20() const363 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
isBDAddr64Disp12() const364 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
isBDAddr64Disp20() const365 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
isBDXAddr64Disp12() const366 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
isBDXAddr64Disp20() const367 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
isBDLAddr64Disp12Len4() const368 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
isBDLAddr64Disp12Len8() const369 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
isBDRAddr64Disp12() const370 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
isBDVAddr64Disp12() const371 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
isU1Imm() const372 bool isU1Imm() const { return isImm(0, 1); }
isU2Imm() const373 bool isU2Imm() const { return isImm(0, 3); }
isU3Imm() const374 bool isU3Imm() const { return isImm(0, 7); }
isU4Imm() const375 bool isU4Imm() const { return isImm(0, 15); }
isU6Imm() const376 bool isU6Imm() const { return isImm(0, 63); }
isU8Imm() const377 bool isU8Imm() const { return isImm(0, 255); }
isS8Imm() const378 bool isS8Imm() const { return isImm(-128, 127); }
isU12Imm() const379 bool isU12Imm() const { return isImm(0, 4095); }
isU16Imm() const380 bool isU16Imm() const { return isImm(0, 65535); }
isS16Imm() const381 bool isS16Imm() const { return isImm(-32768, 32767); }
isU32Imm() const382 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
isS32Imm() const383 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
isU48Imm() const384 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
385 };
386
387 class SystemZAsmParser : public MCTargetAsmParser {
388 #define GET_ASSEMBLER_HEADER
389 #include "SystemZGenAsmMatcher.inc"
390
391 private:
392 MCAsmParser &Parser;
393 enum RegisterGroup {
394 RegGR,
395 RegFP,
396 RegV,
397 RegAR,
398 RegCR
399 };
400 struct Register {
401 RegisterGroup Group;
402 unsigned Num;
403 SMLoc StartLoc, EndLoc;
404 };
405
406 bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
407
408 bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
409
410 OperandMatchResultTy parseRegister(OperandVector &Operands,
411 RegisterKind Kind);
412
413 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
414
415 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
416 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
417 bool HasLength = false, bool HasVectorIndex = false);
418 bool parseAddressRegister(Register &Reg);
419
420 bool ParseDirectiveInsn(SMLoc L);
421
422 OperandMatchResultTy parseAddress(OperandVector &Operands,
423 MemoryKind MemKind,
424 RegisterKind RegKind);
425
426 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
427 int64_t MaxVal, bool AllowTLS);
428
429 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
430
431 public:
SystemZAsmParser(const MCSubtargetInfo & sti,MCAsmParser & parser,const MCInstrInfo & MII,const MCTargetOptions & Options)432 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
433 const MCInstrInfo &MII,
434 const MCTargetOptions &Options)
435 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
436 MCAsmParserExtension::Initialize(Parser);
437
438 // Alias the .word directive to .short.
439 parser.addAliasForDirective(".word", ".short");
440
441 // Initialize the set of available features.
442 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
443 }
444
445 // Override MCTargetAsmParser.
446 bool ParseDirective(AsmToken DirectiveID) override;
447 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
448 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
449 bool RestoreOnFailure);
450 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
451 SMLoc &EndLoc) override;
452 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453 SMLoc NameLoc, OperandVector &Operands) override;
454 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455 OperandVector &Operands, MCStreamer &Out,
456 uint64_t &ErrorInfo,
457 bool MatchingInlineAsm) override;
458
459 // Used by the TableGen code to parse particular operand types.
parseGR32(OperandVector & Operands)460 OperandMatchResultTy parseGR32(OperandVector &Operands) {
461 return parseRegister(Operands, GR32Reg);
462 }
parseGRH32(OperandVector & Operands)463 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464 return parseRegister(Operands, GRH32Reg);
465 }
parseGRX32(OperandVector & Operands)466 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467 llvm_unreachable("GRX32 should only be used for pseudo instructions");
468 }
parseGR64(OperandVector & Operands)469 OperandMatchResultTy parseGR64(OperandVector &Operands) {
470 return parseRegister(Operands, GR64Reg);
471 }
parseGR128(OperandVector & Operands)472 OperandMatchResultTy parseGR128(OperandVector &Operands) {
473 return parseRegister(Operands, GR128Reg);
474 }
parseADDR32(OperandVector & Operands)475 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476 // For the AsmParser, we will accept %r0 for ADDR32 as well.
477 return parseRegister(Operands, GR32Reg);
478 }
parseADDR64(OperandVector & Operands)479 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
480 // For the AsmParser, we will accept %r0 for ADDR64 as well.
481 return parseRegister(Operands, GR64Reg);
482 }
parseADDR128(OperandVector & Operands)483 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
484 llvm_unreachable("Shouldn't be used as an operand");
485 }
parseFP32(OperandVector & Operands)486 OperandMatchResultTy parseFP32(OperandVector &Operands) {
487 return parseRegister(Operands, FP32Reg);
488 }
parseFP64(OperandVector & Operands)489 OperandMatchResultTy parseFP64(OperandVector &Operands) {
490 return parseRegister(Operands, FP64Reg);
491 }
parseFP128(OperandVector & Operands)492 OperandMatchResultTy parseFP128(OperandVector &Operands) {
493 return parseRegister(Operands, FP128Reg);
494 }
parseVR32(OperandVector & Operands)495 OperandMatchResultTy parseVR32(OperandVector &Operands) {
496 return parseRegister(Operands, VR32Reg);
497 }
parseVR64(OperandVector & Operands)498 OperandMatchResultTy parseVR64(OperandVector &Operands) {
499 return parseRegister(Operands, VR64Reg);
500 }
parseVF128(OperandVector & Operands)501 OperandMatchResultTy parseVF128(OperandVector &Operands) {
502 llvm_unreachable("Shouldn't be used as an operand");
503 }
parseVR128(OperandVector & Operands)504 OperandMatchResultTy parseVR128(OperandVector &Operands) {
505 return parseRegister(Operands, VR128Reg);
506 }
parseAR32(OperandVector & Operands)507 OperandMatchResultTy parseAR32(OperandVector &Operands) {
508 return parseRegister(Operands, AR32Reg);
509 }
parseCR64(OperandVector & Operands)510 OperandMatchResultTy parseCR64(OperandVector &Operands) {
511 return parseRegister(Operands, CR64Reg);
512 }
parseAnyReg(OperandVector & Operands)513 OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
514 return parseAnyRegister(Operands);
515 }
parseBDAddr32(OperandVector & Operands)516 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
517 return parseAddress(Operands, BDMem, GR32Reg);
518 }
parseBDAddr64(OperandVector & Operands)519 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
520 return parseAddress(Operands, BDMem, GR64Reg);
521 }
parseBDXAddr64(OperandVector & Operands)522 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
523 return parseAddress(Operands, BDXMem, GR64Reg);
524 }
parseBDLAddr64(OperandVector & Operands)525 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
526 return parseAddress(Operands, BDLMem, GR64Reg);
527 }
parseBDRAddr64(OperandVector & Operands)528 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
529 return parseAddress(Operands, BDRMem, GR64Reg);
530 }
parseBDVAddr64(OperandVector & Operands)531 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
532 return parseAddress(Operands, BDVMem, GR64Reg);
533 }
parsePCRel12(OperandVector & Operands)534 OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
535 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
536 }
parsePCRel16(OperandVector & Operands)537 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
538 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
539 }
parsePCRel24(OperandVector & Operands)540 OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
541 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
542 }
parsePCRel32(OperandVector & Operands)543 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
544 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
545 }
parsePCRelTLS16(OperandVector & Operands)546 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
547 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
548 }
parsePCRelTLS32(OperandVector & Operands)549 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
550 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
551 }
552 };
553
554 } // end anonymous namespace
555
556 #define GET_REGISTER_MATCHER
557 #define GET_SUBTARGET_FEATURE_NAME
558 #define GET_MATCHER_IMPLEMENTATION
559 #define GET_MNEMONIC_SPELL_CHECKER
560 #include "SystemZGenAsmMatcher.inc"
561
562 // Used for the .insn directives; contains information needed to parse the
563 // operands in the directive.
564 struct InsnMatchEntry {
565 StringRef Format;
566 uint64_t Opcode;
567 int32_t NumOperands;
568 MatchClassKind OperandKinds[7];
569 };
570
571 // For equal_range comparison.
572 struct CompareInsn {
operator ()CompareInsn573 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
574 return LHS.Format < RHS;
575 }
operator ()CompareInsn576 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
577 return LHS < RHS.Format;
578 }
operator ()CompareInsn579 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
580 return LHS.Format < RHS.Format;
581 }
582 };
583
584 // Table initializing information for parsing the .insn directive.
585 static struct InsnMatchEntry InsnMatchTable[] = {
586 /* Format, Opcode, NumOperands, OperandKinds */
587 { "e", SystemZ::InsnE, 1,
588 { MCK_U16Imm } },
589 { "ri", SystemZ::InsnRI, 3,
590 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
591 { "rie", SystemZ::InsnRIE, 4,
592 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
593 { "ril", SystemZ::InsnRIL, 3,
594 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
595 { "rilu", SystemZ::InsnRILU, 3,
596 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
597 { "ris", SystemZ::InsnRIS, 5,
598 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
599 { "rr", SystemZ::InsnRR, 3,
600 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
601 { "rre", SystemZ::InsnRRE, 3,
602 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
603 { "rrf", SystemZ::InsnRRF, 5,
604 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
605 { "rrs", SystemZ::InsnRRS, 5,
606 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
607 { "rs", SystemZ::InsnRS, 4,
608 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609 { "rse", SystemZ::InsnRSE, 4,
610 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
611 { "rsi", SystemZ::InsnRSI, 4,
612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
613 { "rsy", SystemZ::InsnRSY, 4,
614 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
615 { "rx", SystemZ::InsnRX, 3,
616 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617 { "rxe", SystemZ::InsnRXE, 3,
618 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619 { "rxf", SystemZ::InsnRXF, 4,
620 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
621 { "rxy", SystemZ::InsnRXY, 3,
622 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
623 { "s", SystemZ::InsnS, 2,
624 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
625 { "si", SystemZ::InsnSI, 3,
626 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
627 { "sil", SystemZ::InsnSIL, 3,
628 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
629 { "siy", SystemZ::InsnSIY, 3,
630 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
631 { "ss", SystemZ::InsnSS, 4,
632 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
633 { "sse", SystemZ::InsnSSE, 3,
634 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
635 { "ssf", SystemZ::InsnSSF, 4,
636 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
637 { "vri", SystemZ::InsnVRI, 6,
638 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
639 { "vrr", SystemZ::InsnVRR, 7,
640 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
641 MCK_U4Imm } },
642 { "vrs", SystemZ::InsnVRS, 5,
643 { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
644 { "vrv", SystemZ::InsnVRV, 4,
645 { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
646 { "vrx", SystemZ::InsnVRX, 4,
647 { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
648 { "vsi", SystemZ::InsnVSI, 4,
649 { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
650 };
651
printMCExpr(const MCExpr * E,raw_ostream & OS)652 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
653 if (!E)
654 return;
655 if (auto *CE = dyn_cast<MCConstantExpr>(E))
656 OS << *CE;
657 else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
658 OS << *UE;
659 else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
660 OS << *BE;
661 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
662 OS << *SRE;
663 else
664 OS << *E;
665 }
666
print(raw_ostream & OS) const667 void SystemZOperand::print(raw_ostream &OS) const {
668 switch (Kind) {
669 case KindToken:
670 OS << "Token:" << getToken();
671 break;
672 case KindReg:
673 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
674 break;
675 case KindImm:
676 OS << "Imm:";
677 printMCExpr(getImm(), OS);
678 break;
679 case KindImmTLS:
680 OS << "ImmTLS:";
681 printMCExpr(getImmTLS().Imm, OS);
682 if (getImmTLS().Sym) {
683 OS << ", ";
684 printMCExpr(getImmTLS().Sym, OS);
685 }
686 break;
687 case KindMem: {
688 const MemOp &Op = getMem();
689 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
690 if (Op.Base) {
691 OS << "(";
692 if (Op.MemKind == BDLMem)
693 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
694 else if (Op.MemKind == BDRMem)
695 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
696 if (Op.Index)
697 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
698 OS << SystemZInstPrinter::getRegisterName(Op.Base);
699 OS << ")";
700 }
701 break;
702 }
703 case KindInvalid:
704 break;
705 }
706 }
707
708 // Parse one register of the form %<prefix><number>.
parseRegister(Register & Reg,bool RestoreOnFailure)709 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
710 Reg.StartLoc = Parser.getTok().getLoc();
711
712 // Eat the % prefix.
713 if (Parser.getTok().isNot(AsmToken::Percent))
714 return Error(Parser.getTok().getLoc(), "register expected");
715 const AsmToken &PercentTok = Parser.getTok();
716 Parser.Lex();
717
718 // Expect a register name.
719 if (Parser.getTok().isNot(AsmToken::Identifier)) {
720 if (RestoreOnFailure)
721 getLexer().UnLex(PercentTok);
722 return Error(Reg.StartLoc, "invalid register");
723 }
724
725 // Check that there's a prefix.
726 StringRef Name = Parser.getTok().getString();
727 if (Name.size() < 2) {
728 if (RestoreOnFailure)
729 getLexer().UnLex(PercentTok);
730 return Error(Reg.StartLoc, "invalid register");
731 }
732 char Prefix = Name[0];
733
734 // Treat the rest of the register name as a register number.
735 if (Name.substr(1).getAsInteger(10, Reg.Num)) {
736 if (RestoreOnFailure)
737 getLexer().UnLex(PercentTok);
738 return Error(Reg.StartLoc, "invalid register");
739 }
740
741 // Look for valid combinations of prefix and number.
742 if (Prefix == 'r' && Reg.Num < 16)
743 Reg.Group = RegGR;
744 else if (Prefix == 'f' && Reg.Num < 16)
745 Reg.Group = RegFP;
746 else if (Prefix == 'v' && Reg.Num < 32)
747 Reg.Group = RegV;
748 else if (Prefix == 'a' && Reg.Num < 16)
749 Reg.Group = RegAR;
750 else if (Prefix == 'c' && Reg.Num < 16)
751 Reg.Group = RegCR;
752 else {
753 if (RestoreOnFailure)
754 getLexer().UnLex(PercentTok);
755 return Error(Reg.StartLoc, "invalid register");
756 }
757
758 Reg.EndLoc = Parser.getTok().getLoc();
759 Parser.Lex();
760 return false;
761 }
762
763 // Parse a register of kind Kind and add it to Operands.
764 OperandMatchResultTy
parseRegister(OperandVector & Operands,RegisterKind Kind)765 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
766 Register Reg;
767 RegisterGroup Group;
768 switch (Kind) {
769 case GR32Reg:
770 case GRH32Reg:
771 case GR64Reg:
772 case GR128Reg:
773 Group = RegGR;
774 break;
775 case FP32Reg:
776 case FP64Reg:
777 case FP128Reg:
778 Group = RegFP;
779 break;
780 case VR32Reg:
781 case VR64Reg:
782 case VR128Reg:
783 Group = RegV;
784 break;
785 case AR32Reg:
786 Group = RegAR;
787 break;
788 case CR64Reg:
789 Group = RegCR;
790 break;
791 }
792
793 // Handle register names of the form %<prefix><number>
794 if (Parser.getTok().is(AsmToken::Percent)) {
795 if (parseRegister(Reg))
796 return MatchOperand_ParseFail;
797
798 // Check the parsed register group "Reg.Group" with the expected "Group"
799 // Have to error out if user specified wrong prefix.
800 switch (Group) {
801 case RegGR:
802 case RegFP:
803 case RegAR:
804 case RegCR:
805 if (Group != Reg.Group) {
806 Error(Reg.StartLoc, "invalid operand for instruction");
807 return MatchOperand_ParseFail;
808 }
809 break;
810 case RegV:
811 if (Reg.Group != RegV && Reg.Group != RegFP) {
812 Error(Reg.StartLoc, "invalid operand for instruction");
813 return MatchOperand_ParseFail;
814 }
815 break;
816 }
817 } else if (Parser.getTok().is(AsmToken::Integer)) {
818 if (parseIntegerRegister(Reg, Group))
819 return MatchOperand_ParseFail;
820 }
821 // Otherwise we didn't match a register operand.
822 else
823 return MatchOperand_NoMatch;
824
825 // Determine the LLVM register number according to Kind.
826 const unsigned *Regs;
827 switch (Kind) {
828 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
829 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
830 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
831 case GR128Reg: Regs = SystemZMC::GR128Regs; break;
832 case FP32Reg: Regs = SystemZMC::FP32Regs; break;
833 case FP64Reg: Regs = SystemZMC::FP64Regs; break;
834 case FP128Reg: Regs = SystemZMC::FP128Regs; break;
835 case VR32Reg: Regs = SystemZMC::VR32Regs; break;
836 case VR64Reg: Regs = SystemZMC::VR64Regs; break;
837 case VR128Reg: Regs = SystemZMC::VR128Regs; break;
838 case AR32Reg: Regs = SystemZMC::AR32Regs; break;
839 case CR64Reg: Regs = SystemZMC::CR64Regs; break;
840 }
841 if (Regs[Reg.Num] == 0) {
842 Error(Reg.StartLoc, "invalid register pair");
843 return MatchOperand_ParseFail;
844 }
845
846 Operands.push_back(
847 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
848 return MatchOperand_Success;
849 }
850
851 // Parse any type of register (including integers) and add it to Operands.
852 OperandMatchResultTy
parseAnyRegister(OperandVector & Operands)853 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
854 SMLoc StartLoc = Parser.getTok().getLoc();
855
856 // Handle integer values.
857 if (Parser.getTok().is(AsmToken::Integer)) {
858 const MCExpr *Register;
859 if (Parser.parseExpression(Register))
860 return MatchOperand_ParseFail;
861
862 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
863 int64_t Value = CE->getValue();
864 if (Value < 0 || Value > 15) {
865 Error(StartLoc, "invalid register");
866 return MatchOperand_ParseFail;
867 }
868 }
869
870 SMLoc EndLoc =
871 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
872
873 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
874 }
875 else {
876 Register Reg;
877 if (parseRegister(Reg))
878 return MatchOperand_ParseFail;
879
880 if (Reg.Num > 15) {
881 Error(StartLoc, "invalid register");
882 return MatchOperand_ParseFail;
883 }
884
885 // Map to the correct register kind.
886 RegisterKind Kind;
887 unsigned RegNo;
888 if (Reg.Group == RegGR) {
889 Kind = GR64Reg;
890 RegNo = SystemZMC::GR64Regs[Reg.Num];
891 }
892 else if (Reg.Group == RegFP) {
893 Kind = FP64Reg;
894 RegNo = SystemZMC::FP64Regs[Reg.Num];
895 }
896 else if (Reg.Group == RegV) {
897 Kind = VR128Reg;
898 RegNo = SystemZMC::VR128Regs[Reg.Num];
899 }
900 else if (Reg.Group == RegAR) {
901 Kind = AR32Reg;
902 RegNo = SystemZMC::AR32Regs[Reg.Num];
903 }
904 else if (Reg.Group == RegCR) {
905 Kind = CR64Reg;
906 RegNo = SystemZMC::CR64Regs[Reg.Num];
907 }
908 else {
909 return MatchOperand_ParseFail;
910 }
911
912 Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
913 Reg.StartLoc, Reg.EndLoc));
914 }
915 return MatchOperand_Success;
916 }
917
parseIntegerRegister(Register & Reg,RegisterGroup Group)918 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
919 RegisterGroup Group) {
920 Reg.StartLoc = Parser.getTok().getLoc();
921 // We have an integer token
922 const MCExpr *Register;
923 if (Parser.parseExpression(Register))
924 return true;
925
926 const auto *CE = dyn_cast<MCConstantExpr>(Register);
927 if (!CE)
928 return true;
929
930 int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
931 int64_t Value = CE->getValue();
932 if (Value < 0 || Value > MaxRegNum) {
933 Error(Parser.getTok().getLoc(), "invalid register");
934 return true;
935 }
936
937 // Assign the Register Number
938 Reg.Num = (unsigned)Value;
939 Reg.Group = Group;
940 Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
941
942 // At this point, successfully parsed an integer register.
943 return false;
944 }
945
946 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
parseAddress(bool & HaveReg1,Register & Reg1,bool & HaveReg2,Register & Reg2,const MCExpr * & Disp,const MCExpr * & Length,bool HasLength,bool HasVectorIndex)947 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
948 bool &HaveReg2, Register &Reg2,
949 const MCExpr *&Disp, const MCExpr *&Length,
950 bool HasLength, bool HasVectorIndex) {
951 // Parse the displacement, which must always be present.
952 if (getParser().parseExpression(Disp))
953 return true;
954
955 // Parse the optional base and index.
956 HaveReg1 = false;
957 HaveReg2 = false;
958 Length = nullptr;
959
960 // If we have a scenario as below:
961 // vgef %v0, 0(0), 0
962 // This is an example of a "BDVMem" instruction type.
963 //
964 // So when we parse this as an integer register, the register group
965 // needs to be tied to "RegV". Usually when the prefix is passed in
966 // as %<prefix><reg-number> its easy to check which group it should belong to
967 // However, if we're passing in just the integer there's no real way to
968 // "check" what register group it should belong to.
969 //
970 // When the user passes in the register as an integer, the user assumes that
971 // the compiler is responsible for substituting it as the right kind of
972 // register. Whereas, when the user specifies a "prefix", the onus is on
973 // the user to make sure they pass in the right kind of register.
974 //
975 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
976 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
977 // (i.e. insn is of type BDVMem) is true.
978 RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
979
980 if (getLexer().is(AsmToken::LParen)) {
981 Parser.Lex();
982
983 if (getLexer().is(AsmToken::Percent)) {
984 // Parse the first register.
985 HaveReg1 = true;
986 if (parseRegister(Reg1))
987 return true;
988 }
989 // So if we have an integer as the first token in ([tok1], ..), it could:
990 // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
991 // instructions)
992 // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
993 else if (getLexer().is(AsmToken::Integer)) {
994 if (HasLength) {
995 // Instruction has a "Length" field, safe to parse the first token as
996 // the "Length" field
997 if (getParser().parseExpression(Length))
998 return true;
999 } else {
1000 // Otherwise, if the instruction has no "Length" field, parse the
1001 // token as a "Register". We don't have to worry about whether the
1002 // instruction is invalid here, because the caller will take care of
1003 // error reporting.
1004 HaveReg1 = true;
1005 if (parseIntegerRegister(Reg1, RegGroup))
1006 return true;
1007 }
1008 } else {
1009 // If its not an integer or a percent token, then if the instruction
1010 // is reported to have a "Length" then, parse it as "Length".
1011 if (HasLength) {
1012 if (getParser().parseExpression(Length))
1013 return true;
1014 }
1015 }
1016
1017 // Check whether there's a second register.
1018 if (getLexer().is(AsmToken::Comma)) {
1019 Parser.Lex();
1020 HaveReg2 = true;
1021
1022 if (getLexer().is(AsmToken::Integer)) {
1023 if (parseIntegerRegister(Reg2, RegGR))
1024 return true;
1025 } else {
1026 if (parseRegister(Reg2))
1027 return true;
1028 }
1029 }
1030
1031 // Consume the closing bracket.
1032 if (getLexer().isNot(AsmToken::RParen))
1033 return Error(Parser.getTok().getLoc(), "unexpected token in address");
1034 Parser.Lex();
1035 }
1036 return false;
1037 }
1038
1039 // Verify that Reg is a valid address register (base or index).
1040 bool
parseAddressRegister(Register & Reg)1041 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1042 if (Reg.Group == RegV) {
1043 Error(Reg.StartLoc, "invalid use of vector addressing");
1044 return true;
1045 } else if (Reg.Group != RegGR) {
1046 Error(Reg.StartLoc, "invalid address register");
1047 return true;
1048 }
1049 return false;
1050 }
1051
1052 // Parse a memory operand and add it to Operands. The other arguments
1053 // are as above.
1054 OperandMatchResultTy
parseAddress(OperandVector & Operands,MemoryKind MemKind,RegisterKind RegKind)1055 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1056 RegisterKind RegKind) {
1057 SMLoc StartLoc = Parser.getTok().getLoc();
1058 unsigned Base = 0, Index = 0, LengthReg = 0;
1059 Register Reg1, Reg2;
1060 bool HaveReg1, HaveReg2;
1061 const MCExpr *Disp;
1062 const MCExpr *Length;
1063
1064 bool HasLength = (MemKind == BDLMem) ? true : false;
1065 bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1066 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1067 HasVectorIndex))
1068 return MatchOperand_ParseFail;
1069
1070 const unsigned *Regs;
1071 switch (RegKind) {
1072 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1073 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1074 default: llvm_unreachable("invalid RegKind");
1075 }
1076
1077 switch (MemKind) {
1078 case BDMem:
1079 // If we have Reg1, it must be an address register.
1080 if (HaveReg1) {
1081 if (parseAddressRegister(Reg1))
1082 return MatchOperand_ParseFail;
1083 Base = Regs[Reg1.Num];
1084 }
1085 // There must be no Reg2.
1086 if (HaveReg2) {
1087 Error(StartLoc, "invalid use of indexed addressing");
1088 return MatchOperand_ParseFail;
1089 }
1090 break;
1091 case BDXMem:
1092 // If we have Reg1, it must be an address register.
1093 if (HaveReg1) {
1094 if (parseAddressRegister(Reg1))
1095 return MatchOperand_ParseFail;
1096 // If the are two registers, the first one is the index and the
1097 // second is the base.
1098 if (HaveReg2)
1099 Index = Regs[Reg1.Num];
1100 else
1101 Base = Regs[Reg1.Num];
1102 }
1103 // If we have Reg2, it must be an address register.
1104 if (HaveReg2) {
1105 if (parseAddressRegister(Reg2))
1106 return MatchOperand_ParseFail;
1107 Base = Regs[Reg2.Num];
1108 }
1109 break;
1110 case BDLMem:
1111 // If we have Reg2, it must be an address register.
1112 if (HaveReg2) {
1113 if (parseAddressRegister(Reg2))
1114 return MatchOperand_ParseFail;
1115 Base = Regs[Reg2.Num];
1116 }
1117 // We cannot support base+index addressing.
1118 if (HaveReg1 && HaveReg2) {
1119 Error(StartLoc, "invalid use of indexed addressing");
1120 return MatchOperand_ParseFail;
1121 }
1122 // We must have a length.
1123 if (!Length) {
1124 Error(StartLoc, "missing length in address");
1125 return MatchOperand_ParseFail;
1126 }
1127 break;
1128 case BDRMem:
1129 // We must have Reg1, and it must be a GPR.
1130 if (!HaveReg1 || Reg1.Group != RegGR) {
1131 Error(StartLoc, "invalid operand for instruction");
1132 return MatchOperand_ParseFail;
1133 }
1134 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1135 // If we have Reg2, it must be an address register.
1136 if (HaveReg2) {
1137 if (parseAddressRegister(Reg2))
1138 return MatchOperand_ParseFail;
1139 Base = Regs[Reg2.Num];
1140 }
1141 break;
1142 case BDVMem:
1143 // We must have Reg1, and it must be a vector register.
1144 if (!HaveReg1 || Reg1.Group != RegV) {
1145 Error(StartLoc, "vector index required in address");
1146 return MatchOperand_ParseFail;
1147 }
1148 Index = SystemZMC::VR128Regs[Reg1.Num];
1149 // If we have Reg2, it must be an address register.
1150 if (HaveReg2) {
1151 if (parseAddressRegister(Reg2))
1152 return MatchOperand_ParseFail;
1153 Base = Regs[Reg2.Num];
1154 }
1155 break;
1156 }
1157
1158 SMLoc EndLoc =
1159 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1160 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1161 Index, Length, LengthReg,
1162 StartLoc, EndLoc));
1163 return MatchOperand_Success;
1164 }
1165
ParseDirective(AsmToken DirectiveID)1166 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1167 StringRef IDVal = DirectiveID.getIdentifier();
1168
1169 if (IDVal == ".insn")
1170 return ParseDirectiveInsn(DirectiveID.getLoc());
1171
1172 return true;
1173 }
1174
1175 /// ParseDirectiveInsn
1176 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
ParseDirectiveInsn(SMLoc L)1177 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1178 MCAsmParser &Parser = getParser();
1179
1180 // Expect instruction format as identifier.
1181 StringRef Format;
1182 SMLoc ErrorLoc = Parser.getTok().getLoc();
1183 if (Parser.parseIdentifier(Format))
1184 return Error(ErrorLoc, "expected instruction format");
1185
1186 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1187
1188 // Find entry for this format in InsnMatchTable.
1189 auto EntryRange =
1190 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1191 Format, CompareInsn());
1192
1193 // If first == second, couldn't find a match in the table.
1194 if (EntryRange.first == EntryRange.second)
1195 return Error(ErrorLoc, "unrecognized format");
1196
1197 struct InsnMatchEntry *Entry = EntryRange.first;
1198
1199 // Format should match from equal_range.
1200 assert(Entry->Format == Format);
1201
1202 // Parse the following operands using the table's information.
1203 for (int i = 0; i < Entry->NumOperands; i++) {
1204 MatchClassKind Kind = Entry->OperandKinds[i];
1205
1206 SMLoc StartLoc = Parser.getTok().getLoc();
1207
1208 // Always expect commas as separators for operands.
1209 if (getLexer().isNot(AsmToken::Comma))
1210 return Error(StartLoc, "unexpected token in directive");
1211 Lex();
1212
1213 // Parse operands.
1214 OperandMatchResultTy ResTy;
1215 if (Kind == MCK_AnyReg)
1216 ResTy = parseAnyReg(Operands);
1217 else if (Kind == MCK_VR128)
1218 ResTy = parseVR128(Operands);
1219 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1220 ResTy = parseBDXAddr64(Operands);
1221 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1222 ResTy = parseBDAddr64(Operands);
1223 else if (Kind == MCK_BDVAddr64Disp12)
1224 ResTy = parseBDVAddr64(Operands);
1225 else if (Kind == MCK_PCRel32)
1226 ResTy = parsePCRel32(Operands);
1227 else if (Kind == MCK_PCRel16)
1228 ResTy = parsePCRel16(Operands);
1229 else {
1230 // Only remaining operand kind is an immediate.
1231 const MCExpr *Expr;
1232 SMLoc StartLoc = Parser.getTok().getLoc();
1233
1234 // Expect immediate expression.
1235 if (Parser.parseExpression(Expr))
1236 return Error(StartLoc, "unexpected token in directive");
1237
1238 SMLoc EndLoc =
1239 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1240
1241 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1242 ResTy = MatchOperand_Success;
1243 }
1244
1245 if (ResTy != MatchOperand_Success)
1246 return true;
1247 }
1248
1249 // Build the instruction with the parsed operands.
1250 MCInst Inst = MCInstBuilder(Entry->Opcode);
1251
1252 for (size_t i = 0; i < Operands.size(); i++) {
1253 MCParsedAsmOperand &Operand = *Operands[i];
1254 MatchClassKind Kind = Entry->OperandKinds[i];
1255
1256 // Verify operand.
1257 unsigned Res = validateOperandClass(Operand, Kind);
1258 if (Res != Match_Success)
1259 return Error(Operand.getStartLoc(), "unexpected operand type");
1260
1261 // Add operands to instruction.
1262 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1263 if (ZOperand.isReg())
1264 ZOperand.addRegOperands(Inst, 1);
1265 else if (ZOperand.isMem(BDMem))
1266 ZOperand.addBDAddrOperands(Inst, 2);
1267 else if (ZOperand.isMem(BDXMem))
1268 ZOperand.addBDXAddrOperands(Inst, 3);
1269 else if (ZOperand.isMem(BDVMem))
1270 ZOperand.addBDVAddrOperands(Inst, 3);
1271 else if (ZOperand.isImm())
1272 ZOperand.addImmOperands(Inst, 1);
1273 else
1274 llvm_unreachable("unexpected operand type");
1275 }
1276
1277 // Emit as a regular instruction.
1278 Parser.getStreamer().emitInstruction(Inst, getSTI());
1279
1280 return false;
1281 }
1282
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc,bool RestoreOnFailure)1283 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1284 SMLoc &EndLoc, bool RestoreOnFailure) {
1285 Register Reg;
1286 if (parseRegister(Reg, RestoreOnFailure))
1287 return true;
1288 if (Reg.Group == RegGR)
1289 RegNo = SystemZMC::GR64Regs[Reg.Num];
1290 else if (Reg.Group == RegFP)
1291 RegNo = SystemZMC::FP64Regs[Reg.Num];
1292 else if (Reg.Group == RegV)
1293 RegNo = SystemZMC::VR128Regs[Reg.Num];
1294 else if (Reg.Group == RegAR)
1295 RegNo = SystemZMC::AR32Regs[Reg.Num];
1296 else if (Reg.Group == RegCR)
1297 RegNo = SystemZMC::CR64Regs[Reg.Num];
1298 StartLoc = Reg.StartLoc;
1299 EndLoc = Reg.EndLoc;
1300 return false;
1301 }
1302
ParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)1303 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1304 SMLoc &EndLoc) {
1305 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1306 }
1307
tryParseRegister(unsigned & RegNo,SMLoc & StartLoc,SMLoc & EndLoc)1308 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1309 SMLoc &StartLoc,
1310 SMLoc &EndLoc) {
1311 bool Result =
1312 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1313 bool PendingErrors = getParser().hasPendingError();
1314 getParser().clearPendingErrors();
1315 if (PendingErrors)
1316 return MatchOperand_ParseFail;
1317 if (Result)
1318 return MatchOperand_NoMatch;
1319 return MatchOperand_Success;
1320 }
1321
ParseInstruction(ParseInstructionInfo & Info,StringRef Name,SMLoc NameLoc,OperandVector & Operands)1322 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1323 StringRef Name, SMLoc NameLoc,
1324 OperandVector &Operands) {
1325
1326 // Apply mnemonic aliases first, before doing anything else, in
1327 // case the target uses it.
1328 applyMnemonicAliases(Name, getAvailableFeatures(), 0 /*VariantID*/);
1329
1330 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1331
1332 // Read the remaining operands.
1333 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1334 // Read the first operand.
1335 if (parseOperand(Operands, Name)) {
1336 return true;
1337 }
1338
1339 // Read any subsequent operands.
1340 while (getLexer().is(AsmToken::Comma)) {
1341 Parser.Lex();
1342 if (parseOperand(Operands, Name)) {
1343 return true;
1344 }
1345 }
1346 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1347 SMLoc Loc = getLexer().getLoc();
1348 return Error(Loc, "unexpected token in argument list");
1349 }
1350 }
1351
1352 // Consume the EndOfStatement.
1353 Parser.Lex();
1354 return false;
1355 }
1356
parseOperand(OperandVector & Operands,StringRef Mnemonic)1357 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1358 StringRef Mnemonic) {
1359 // Check if the current operand has a custom associated parser, if so, try to
1360 // custom parse the operand, or fallback to the general approach. Force all
1361 // features to be available during the operand check, or else we will fail to
1362 // find the custom parser, and then we will later get an InvalidOperand error
1363 // instead of a MissingFeature errror.
1364 FeatureBitset AvailableFeatures = getAvailableFeatures();
1365 FeatureBitset All;
1366 All.set();
1367 setAvailableFeatures(All);
1368 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1369 setAvailableFeatures(AvailableFeatures);
1370 if (ResTy == MatchOperand_Success)
1371 return false;
1372
1373 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1374 // there was a match, but an error occurred, in which case, just return that
1375 // the operand parsing failed.
1376 if (ResTy == MatchOperand_ParseFail)
1377 return true;
1378
1379 // Check for a register. All real register operands should have used
1380 // a context-dependent parse routine, which gives the required register
1381 // class. The code is here to mop up other cases, like those where
1382 // the instruction isn't recognized.
1383 if (Parser.getTok().is(AsmToken::Percent)) {
1384 Register Reg;
1385 if (parseRegister(Reg))
1386 return true;
1387 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1388 return false;
1389 }
1390
1391 // The only other type of operand is an immediate or address. As above,
1392 // real address operands should have used a context-dependent parse routine,
1393 // so we treat any plain expression as an immediate.
1394 SMLoc StartLoc = Parser.getTok().getLoc();
1395 Register Reg1, Reg2;
1396 bool HaveReg1, HaveReg2;
1397 const MCExpr *Expr;
1398 const MCExpr *Length;
1399 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1400 /*HasLength*/ true, /*HasVectorIndex*/ true))
1401 return true;
1402 // If the register combination is not valid for any instruction, reject it.
1403 // Otherwise, fall back to reporting an unrecognized instruction.
1404 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1405 && parseAddressRegister(Reg1))
1406 return true;
1407 if (HaveReg2 && parseAddressRegister(Reg2))
1408 return true;
1409
1410 SMLoc EndLoc =
1411 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1412 if (HaveReg1 || HaveReg2 || Length)
1413 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1414 else
1415 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1416 return false;
1417 }
1418
1419 static std::string SystemZMnemonicSpellCheck(StringRef S,
1420 const FeatureBitset &FBS,
1421 unsigned VariantID = 0);
1422
MatchAndEmitInstruction(SMLoc IDLoc,unsigned & Opcode,OperandVector & Operands,MCStreamer & Out,uint64_t & ErrorInfo,bool MatchingInlineAsm)1423 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1424 OperandVector &Operands,
1425 MCStreamer &Out,
1426 uint64_t &ErrorInfo,
1427 bool MatchingInlineAsm) {
1428 MCInst Inst;
1429 unsigned MatchResult;
1430
1431 FeatureBitset MissingFeatures;
1432 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1433 MissingFeatures, MatchingInlineAsm);
1434 switch (MatchResult) {
1435 case Match_Success:
1436 Inst.setLoc(IDLoc);
1437 Out.emitInstruction(Inst, getSTI());
1438 return false;
1439
1440 case Match_MissingFeature: {
1441 assert(MissingFeatures.any() && "Unknown missing feature!");
1442 // Special case the error message for the very common case where only
1443 // a single subtarget feature is missing
1444 std::string Msg = "instruction requires:";
1445 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1446 if (MissingFeatures[I]) {
1447 Msg += " ";
1448 Msg += getSubtargetFeatureName(I);
1449 }
1450 }
1451 return Error(IDLoc, Msg);
1452 }
1453
1454 case Match_InvalidOperand: {
1455 SMLoc ErrorLoc = IDLoc;
1456 if (ErrorInfo != ~0ULL) {
1457 if (ErrorInfo >= Operands.size())
1458 return Error(IDLoc, "too few operands for instruction");
1459
1460 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1461 if (ErrorLoc == SMLoc())
1462 ErrorLoc = IDLoc;
1463 }
1464 return Error(ErrorLoc, "invalid operand for instruction");
1465 }
1466
1467 case Match_MnemonicFail: {
1468 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1469 std::string Suggestion = SystemZMnemonicSpellCheck(
1470 ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1471 return Error(IDLoc, "invalid instruction" + Suggestion,
1472 ((SystemZOperand &)*Operands[0]).getLocRange());
1473 }
1474 }
1475
1476 llvm_unreachable("Unexpected match type");
1477 }
1478
1479 OperandMatchResultTy
parsePCRel(OperandVector & Operands,int64_t MinVal,int64_t MaxVal,bool AllowTLS)1480 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1481 int64_t MaxVal, bool AllowTLS) {
1482 MCContext &Ctx = getContext();
1483 MCStreamer &Out = getStreamer();
1484 const MCExpr *Expr;
1485 SMLoc StartLoc = Parser.getTok().getLoc();
1486 if (getParser().parseExpression(Expr))
1487 return MatchOperand_NoMatch;
1488
1489 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1490 if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1491 int64_t Value = CE->getValue();
1492 if ((Value & 1) || Value < MinVal || Value > MaxVal)
1493 return true;
1494 }
1495 return false;
1496 };
1497
1498 // For consistency with the GNU assembler, treat immediates as offsets
1499 // from ".".
1500 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1501 if (isOutOfRangeConstant(CE)) {
1502 Error(StartLoc, "offset out of range");
1503 return MatchOperand_ParseFail;
1504 }
1505 int64_t Value = CE->getValue();
1506 MCSymbol *Sym = Ctx.createTempSymbol();
1507 Out.emitLabel(Sym);
1508 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1509 Ctx);
1510 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1511 }
1512
1513 // For consistency with the GNU assembler, conservatively assume that a
1514 // constant offset must by itself be within the given size range.
1515 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1516 if (isOutOfRangeConstant(BE->getLHS()) ||
1517 isOutOfRangeConstant(BE->getRHS())) {
1518 Error(StartLoc, "offset out of range");
1519 return MatchOperand_ParseFail;
1520 }
1521
1522 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1523 const MCExpr *Sym = nullptr;
1524 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1525 Parser.Lex();
1526
1527 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1528 Error(Parser.getTok().getLoc(), "unexpected token");
1529 return MatchOperand_ParseFail;
1530 }
1531
1532 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1533 StringRef Name = Parser.getTok().getString();
1534 if (Name == "tls_gdcall")
1535 Kind = MCSymbolRefExpr::VK_TLSGD;
1536 else if (Name == "tls_ldcall")
1537 Kind = MCSymbolRefExpr::VK_TLSLDM;
1538 else {
1539 Error(Parser.getTok().getLoc(), "unknown TLS tag");
1540 return MatchOperand_ParseFail;
1541 }
1542 Parser.Lex();
1543
1544 if (Parser.getTok().isNot(AsmToken::Colon)) {
1545 Error(Parser.getTok().getLoc(), "unexpected token");
1546 return MatchOperand_ParseFail;
1547 }
1548 Parser.Lex();
1549
1550 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1551 Error(Parser.getTok().getLoc(), "unexpected token");
1552 return MatchOperand_ParseFail;
1553 }
1554
1555 StringRef Identifier = Parser.getTok().getString();
1556 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1557 Kind, Ctx);
1558 Parser.Lex();
1559 }
1560
1561 SMLoc EndLoc =
1562 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1563
1564 if (AllowTLS)
1565 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1566 StartLoc, EndLoc));
1567 else
1568 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1569
1570 return MatchOperand_Success;
1571 }
1572
1573 // Force static initialization.
LLVMInitializeSystemZAsmParser()1574 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1575 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1576 }
1577