1; RUN: opt -mtriple=amdgcn-- -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
2
3; This test contains an unstructured loop.
4;           +-------------- entry ----------------+
5;           |                                     |
6;           V                                     V
7; i1 = phi(0, i3)                            i2 = phi(0, i3)
8;     j1 = i1 + 1 ---> i3 = phi(j1, j2) <--- j2 = i2 + 2
9;           ^                 |                   ^
10;           |                 V                   |
11;           +-------- switch (tid / i3) ----------+
12;                             |
13;                             V
14;                        if (i3 == 5) // divergent
15; because sync dependent on (tid / i3).
16define i32 @unstructured_loop(i1 %entry_cond) {
17; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'unstructured_loop'
18entry:
19  %tid = call i32 @llvm.amdgcn.workitem.id.x()
20  br i1 %entry_cond, label %loop_entry_1, label %loop_entry_2
21loop_entry_1:
22  %i1 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
23  %j1 = add i32 %i1, 1
24  br label %loop_body
25loop_entry_2:
26  %i2 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
27  %j2 = add i32 %i2, 2
28  br label %loop_body
29loop_body:
30  %i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ]
31  br label %loop_latch
32loop_latch:
33  %div = sdiv i32 %tid, %i3
34  switch i32 %div, label %branch [ i32 1, label %loop_entry_1
35                                   i32 2, label %loop_entry_2 ]
36branch:
37  %cmp = icmp eq i32 %i3, 5
38  br i1 %cmp, label %then, label %else
39; CHECK: DIVERGENT: br i1 %cmp,
40then:
41  ret i32 0
42else:
43  ret i32 1
44}
45
46declare i32 @llvm.amdgcn.workitem.id.x() #0
47
48attributes #0 = { nounwind readnone }
49