1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
3---
4name:            test_loop_phi_fpr_to_gpr
5alignment:       4
6legalized:       true
7regBankSelected: true
8selected:        false
9failedISel:      false
10tracksRegLiveness: true
11liveins:         []
12machineFunctionInfo: {}
13body:             |
14  ; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
15  ; CHECK: bb.0:
16  ; CHECK:   successors: %bb.1(0x80000000)
17  ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
18  ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
19  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
20  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
21  ; CHECK: bb.1:
22  ; CHECK:   successors: %bb.2(0x80000000)
23  ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
24  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
25  ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
26  ; CHECK: bb.2:
27  ; CHECK:   successors: %bb.2(0x80000000)
28  ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
29  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
30  ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
31  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
32  ; CHECK:   STRHHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
33  ; CHECK:   B %bb.2
34  bb.0:
35    successors: %bb.1(0x80000000)
36
37    %0:gpr(s1) = G_IMPLICIT_DEF
38    %4:gpr(p0) = G_IMPLICIT_DEF
39    %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
40
41  bb.1:
42    successors: %bb.2(0x80000000)
43
44    %6:gpr(s32) = G_IMPLICIT_DEF
45    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
46    %1:gpr(s16) = G_TRUNC %7(s32)
47
48  bb.2:
49    successors: %bb.2(0x80000000)
50
51    %3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
52    %5:fpr(s16) = G_FPTRUNC %8(s32)
53    G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
54    G_BR %bb.2
55
56...
57---
58name:            test_loop_phi_gpr_to_fpr
59alignment:       4
60legalized:       true
61regBankSelected: true
62selected:        false
63failedISel:      false
64tracksRegLiveness: true
65liveins:         []
66machineFunctionInfo: {}
67body:             |
68  ; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
69  ; CHECK: bb.0:
70  ; CHECK:   successors: %bb.1(0x80000000)
71  ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
72  ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
73  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
74  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
75  ; CHECK: bb.1:
76  ; CHECK:   successors: %bb.2(0x80000000)
77  ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
78  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
79  ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
80  ; CHECK:   [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
81  ; CHECK:   [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
82  ; CHECK: bb.2:
83  ; CHECK:   successors: %bb.2(0x80000000)
84  ; CHECK:   [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
85  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
86  ; CHECK:   STRHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
87  ; CHECK:   B %bb.2
88  bb.0:
89    successors: %bb.1(0x80000000)
90
91    %0:gpr(s1) = G_IMPLICIT_DEF
92    %4:gpr(p0) = G_IMPLICIT_DEF
93    %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
94
95  bb.1:
96    successors: %bb.2(0x80000000)
97
98    %6:gpr(s32) = G_IMPLICIT_DEF
99    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
100    %1:gpr(s16) = G_TRUNC %7(s32)
101
102  bb.2:
103    successors: %bb.2(0x80000000)
104
105    %3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
106    %5:fpr(s16) = G_FPTRUNC %8(s32)
107    G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
108    G_BR %bb.2
109
110...
111