1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Test G_EXT selection using AArch64ext patterns.
5
6...
7---
8name:            v8s8_EXTv8i8
9alignment:       4
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13body:             |
14  bb.0:
15    liveins: $d0, $d1
16
17    ; CHECK-LABEL: name: v8s8_EXTv8i8
18    ; CHECK: liveins: $d0, $d1
19    ; CHECK: %v1:fpr64 = COPY $d0
20    ; CHECK: %v2:fpr64 = COPY $d1
21    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
22    %v1:fpr(<8 x s8>) = COPY $d0
23    %v2:fpr(<8 x s8>) = COPY $d1
24    %3:gpr(s32) = G_CONSTANT i32 3
25    %shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
26
27...
28---
29name:            v16s8_EXTv16i8
30alignment:       4
31legalized:       true
32regBankSelected: true
33tracksRegLiveness: true
34body:             |
35  bb.0:
36    liveins: $q0, $q1
37
38    ; CHECK-LABEL: name: v16s8_EXTv16i8
39    ; CHECK: liveins: $q0, $q1
40    ; CHECK: %v1:fpr128 = COPY $q0
41    ; CHECK: %v2:fpr128 = COPY $q1
42    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
43    %v1:fpr(<16 x s8>) = COPY $q0
44    %v2:fpr(<16 x s8>) = COPY $q1
45    %3:gpr(s32) = G_CONSTANT i32 3
46    %shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
47
48...
49---
50name:            v4s16_EXTv8i8
51alignment:       4
52legalized:       true
53regBankSelected: true
54tracksRegLiveness: true
55body:             |
56  bb.0:
57    liveins: $d0, $d1
58
59    ; CHECK-LABEL: name: v4s16_EXTv8i8
60    ; CHECK: liveins: $d0, $d1
61    ; CHECK: %v1:fpr64 = COPY $d0
62    ; CHECK: %v2:fpr64 = COPY $d1
63    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
64    %v1:fpr(<4 x s16>) = COPY $d0
65    %v2:fpr(<4 x s16>) = COPY $d1
66    %3:gpr(s32) = G_CONSTANT i32 6
67    %shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
68
69...
70---
71name:            v8s16_EXTv16i8
72alignment:       4
73legalized:       true
74regBankSelected: true
75tracksRegLiveness: true
76body:             |
77  bb.0:
78    liveins: $q0, $q1
79
80    ; CHECK-LABEL: name: v8s16_EXTv16i8
81    ; CHECK: liveins: $q0, $q1
82    ; CHECK: %v1:fpr128 = COPY $q0
83    ; CHECK: %v2:fpr128 = COPY $q1
84    ; CHECK: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
85    %v1:fpr(<8 x s16>) = COPY $q0
86    %v2:fpr(<8 x s16>) = COPY $q1
87    %3:gpr(s32) = G_CONSTANT i32 10
88    %shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
89...
90
91...
92---
93name:            v4s32_EXTv16i8
94alignment:       4
95legalized:       true
96regBankSelected: true
97tracksRegLiveness: true
98body:             |
99  bb.0:
100    liveins: $q0, $q1
101
102    ; CHECK-LABEL: name: v4s32_EXTv16i8
103    ; CHECK: liveins: $q0, $q1
104    ; CHECK: %v1:fpr128 = COPY $q0
105    ; CHECK: %v2:fpr128 = COPY $q1
106    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
107    %v1:fpr(<4 x s32>) = COPY $q0
108    %v2:fpr(<4 x s32>) = COPY $q1
109    %3:gpr(s32) = G_CONSTANT i32 12
110    %shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
111
112...
113---
114name:            v2s32_EXTv8i8
115alignment:       4
116legalized:       true
117regBankSelected: true
118tracksRegLiveness: true
119body:             |
120  bb.0:
121    liveins: $d0, $d1
122
123    ; CHECK-LABEL: name: v2s32_EXTv8i8
124    ; CHECK: liveins: $d0, $d1
125    ; CHECK: %v1:fpr64 = COPY $d0
126    ; CHECK: %v2:fpr64 = COPY $d1
127    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
128    %v1:fpr(<2 x s32>) = COPY $d0
129    %v2:fpr(<2 x s32>) = COPY $d1
130    %3:gpr(s32) = G_CONSTANT i32 2
131    %shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
132
133...
134---
135name:            v2s64_EXTv16i8
136alignment:       4
137legalized:       true
138regBankSelected: true
139tracksRegLiveness: true
140body:             |
141  bb.0:
142    liveins: $q0, $q1
143
144    ; CHECK-LABEL: name: v2s64_EXTv16i8
145    ; CHECK: liveins: $q0, $q1
146    ; CHECK: %v1:fpr128 = COPY $q0
147    ; CHECK: %v2:fpr128 = COPY $q1
148    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
149    %v1:fpr(<2 x s64>) = COPY $q0
150    %v2:fpr(<2 x s64>) = COPY $q1
151    %3:gpr(s32) = G_CONSTANT i32 2
152    %shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
153...
154