1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
3...
4---
5name:            v2s32_fpr
6alignment:       4
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10registers:
11  - { id: 0, class: fpr }
12  - { id: 1, class: fpr }
13  - { id: 2, class: gpr }
14  - { id: 3, class: fpr }
15body:             |
16  bb.0:
17    liveins: $d0
18
19    ; CHECK-LABEL: name: v2s32_fpr
20    ; CHECK: liveins: $d0
21    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
22    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
23    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
24    ; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
25    ; CHECK: $s0 = COPY [[CPYi32_]]
26    ; CHECK: RET_ReallyLR implicit $s0
27    %0:fpr(<2 x s32>) = COPY $d0
28    %2:gpr(s64) = G_CONSTANT i64 1
29    %3:fpr(s64) = COPY %2(s64)
30    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
31    $s0 = COPY %1(s32)
32    RET_ReallyLR implicit $s0
33
34...
35---
36name:            v2s32_fpr_idx0
37alignment:       4
38legalized:       true
39regBankSelected: true
40tracksRegLiveness: true
41body:             |
42  bb.0:
43    liveins: $d0
44    ; CHECK-LABEL: name: v2s32_fpr_idx0
45    ; CHECK: liveins: $d0
46    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
47    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
48    ; CHECK: $s0 = COPY [[COPY1]]
49    ; CHECK: RET_ReallyLR implicit $s0
50    %0:fpr(<2 x s32>) = COPY $d0
51    %2:gpr(s64) = G_CONSTANT i64 0
52    %3:fpr(s64) = COPY %2(s64)
53    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
54    $s0 = COPY %1(s32)
55    RET_ReallyLR implicit $s0
56
57...
58---
59name:            v2s64_fpr
60alignment:       4
61legalized:       true
62regBankSelected: true
63tracksRegLiveness: true
64registers:
65  - { id: 0, class: fpr }
66  - { id: 1, class: fpr }
67  - { id: 2, class: gpr }
68  - { id: 3, class: fpr }
69body:             |
70  bb.0:
71    liveins: $q0
72
73    ; CHECK-LABEL: name: v2s64_fpr
74    ; CHECK: liveins: $q0
75    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
76    ; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 2
77    ; CHECK: $d0 = COPY [[CPYi64_]]
78    ; CHECK: RET_ReallyLR implicit $d0
79    %0:fpr(<2 x s64>) = COPY $q0
80    %2:gpr(s64) = G_CONSTANT i64 2
81    %3:fpr(s64) = COPY %2(s64)
82    %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
83    $d0 = COPY %1(s64)
84    RET_ReallyLR implicit $d0
85
86...
87---
88name:            v4s16_fpr
89alignment:       4
90legalized:       true
91regBankSelected: true
92tracksRegLiveness: true
93registers:
94  - { id: 0, class: fpr }
95  - { id: 1, class: fpr }
96  - { id: 2, class: gpr }
97  - { id: 3, class: fpr }
98body:             |
99  bb.0:
100    liveins: $d0
101
102    ; CHECK-LABEL: name: v4s16_fpr
103    ; CHECK: liveins: $d0
104    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
105    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
106    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
107    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
108    ; CHECK: $h0 = COPY [[CPYi16_]]
109    ; CHECK: RET_ReallyLR implicit $h0
110    %0:fpr(<4 x s16>) = COPY $d0
111    %2:gpr(s64) = G_CONSTANT i64 1
112    %3:fpr(s64) = COPY %2(s64)
113    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
114    $h0 = COPY %1(s16)
115    RET_ReallyLR implicit $h0
116
117...
118---
119name:            v8s16_fpr
120alignment:       4
121legalized:       true
122regBankSelected: true
123tracksRegLiveness: true
124body:             |
125  bb.0:
126    liveins: $q0
127    ; CHECK-LABEL: name: v8s16_fpr
128    ; CHECK: liveins: $q0
129    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
130    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
131    ; CHECK: $h0 = COPY [[CPYi16_]]
132    ; CHECK: RET_ReallyLR implicit $h0
133    %0:fpr(<8 x s16>) = COPY $q0
134    %2:gpr(s64) = G_CONSTANT i64 1
135    %3:fpr(s64) = COPY %2(s64)
136    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
137    $h0 = COPY %1(s16)
138    RET_ReallyLR implicit $h0
139
140...
141---
142name:            v8s16_fpr_zext
143alignment:       4
144legalized:       true
145regBankSelected: true
146tracksRegLiveness: true
147body:             |
148  bb.0:
149    liveins: $q0
150    ; CHECK-LABEL: name: v8s16_fpr_zext
151    ; CHECK: liveins: $q0
152    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
153    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
154    ; CHECK: $h0 = COPY [[CPYi16_]]
155    ; CHECK: RET_ReallyLR implicit $h0
156    %0:fpr(<8 x s16>) = COPY $q0
157    %1:gpr(s32) = G_CONSTANT i32 1
158    %2:gpr(s64) = G_ZEXT %1
159    %3:fpr(s64) = COPY %2(s64)
160    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
161    $h0 = COPY %4(s16)
162    RET_ReallyLR implicit $h0
163
164...
165---
166name:            v8s16_fpr_sext
167alignment:       4
168legalized:       true
169regBankSelected: true
170tracksRegLiveness: true
171body:             |
172  bb.0:
173    liveins: $q0
174    ; CHECK-LABEL: name: v8s16_fpr_sext
175    ; CHECK: liveins: $q0
176    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
177    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
178    ; CHECK: $h0 = COPY [[CPYi16_]]
179    ; CHECK: RET_ReallyLR implicit $h0
180    %0:fpr(<8 x s16>) = COPY $q0
181    %1:gpr(s32) = G_CONSTANT i32 1
182    %2:gpr(s64) = G_SEXT %1
183    %3:fpr(s64) = COPY %2(s64)
184    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
185    $h0 = COPY %4(s16)
186    RET_ReallyLR implicit $h0
187
188...
189---
190name:            v8s16_fpr_trunc
191alignment:       4
192legalized:       true
193regBankSelected: true
194tracksRegLiveness: true
195body:             |
196  bb.0:
197    liveins: $q0
198    ; CHECK-LABEL: name: v8s16_fpr_trunc
199    ; CHECK: liveins: $q0
200    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
201    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
202    ; CHECK: $h0 = COPY [[CPYi16_]]
203    ; CHECK: RET_ReallyLR implicit $h0
204    %0:fpr(<8 x s16>) = COPY $q0
205    %1:gpr(s64) = G_CONSTANT i64 1
206    %2:gpr(s32) = G_TRUNC %1
207    %3:gpr(s64) = G_SEXT %2
208    %4:fpr(s64) = COPY %3(s64)
209    %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
210    $h0 = COPY %5(s16)
211    RET_ReallyLR implicit $h0
212...
213---
214name:            v2p0
215alignment:       4
216legalized:       true
217regBankSelected: true
218tracksRegLiveness: true
219body:             |
220  bb.0:
221    liveins: $q0
222
223    ; CHECK-LABEL: name: v2p0
224    ; CHECK: liveins: $q0
225    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
226    ; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
227    ; CHECK: $d0 = COPY [[CPYi64_]]
228    ; CHECK: RET_ReallyLR implicit $d0
229    %0:fpr(<2 x p0>) = COPY $q0
230    %2:gpr(s64) = G_CONSTANT i64 1
231    %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
232    $d0 = COPY %1(p0)
233    RET_ReallyLR implicit $d0
234
235...
236