1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s
3
4...
5---
6name:            test_f16.rint
7alignment:       4
8legalized:       true
9regBankSelected: true
10tracksRegLiveness: true
11machineFunctionInfo: {}
12body:             |
13  bb.0:
14    liveins: $h0
15
16    ; CHECK-LABEL: name: test_f16.rint
17    ; CHECK: liveins: $h0
18    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
19    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
20    ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
21    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
22    ; CHECK: $h0 = COPY [[FCVTHSr]]
23    ; CHECK: RET_ReallyLR implicit $h0
24    %0:fpr(s16) = COPY $h0
25    %2:fpr(s32) = G_FPEXT %0(s16)
26    %3:fpr(s32) = G_FRINT %2
27    %1:fpr(s16) = G_FPTRUNC %3(s32)
28    $h0 = COPY %1(s16)
29    RET_ReallyLR implicit $h0
30
31...
32---
33name:            test_v4f16.rint
34alignment:       4
35legalized:       true
36regBankSelected: true
37tracksRegLiveness: true
38machineFunctionInfo: {}
39body:             |
40  bb.0:
41    liveins: $d0
42
43    ; CHECK-LABEL: name: test_v4f16.rint
44    ; CHECK: liveins: $d0
45    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
46    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
47    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
48    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
49    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
50    ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
51    ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub
52    ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
53    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1
54    ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2
55    ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3
56    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
57    ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
58    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
59    ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]]
60    ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
61    ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
62    ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]]
63    ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
64    ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
65    ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]]
66    ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
67    ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
68    ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
69    ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub
70    ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
71    ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub
72    ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
73    ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
74    ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub
75    ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
76    ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
77    ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub
78    ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
79    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
80    ; CHECK: $d0 = COPY [[COPY2]]
81    ; CHECK: RET_ReallyLR implicit $d0
82    %0:fpr(<4 x s16>) = COPY $d0
83    %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
84    %16:fpr(s32) = G_FPEXT %2(s16)
85    %17:fpr(s32) = G_FRINT %16
86    %6:fpr(s16) = G_FPTRUNC %17(s32)
87    %14:fpr(s32) = G_FPEXT %3(s16)
88    %15:fpr(s32) = G_FRINT %14
89    %7:fpr(s16) = G_FPTRUNC %15(s32)
90    %12:fpr(s32) = G_FPEXT %4(s16)
91    %13:fpr(s32) = G_FRINT %12
92    %8:fpr(s16) = G_FPTRUNC %13(s32)
93    %10:fpr(s32) = G_FPEXT %5(s16)
94    %11:fpr(s32) = G_FRINT %10
95    %9:fpr(s16) = G_FPTRUNC %11(s32)
96    %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16)
97    $d0 = COPY %1(<4 x s16>)
98    RET_ReallyLR implicit $d0
99
100...
101---
102name:            test_v8f16.rint
103alignment:       4
104legalized:       true
105regBankSelected: true
106tracksRegLiveness: true
107machineFunctionInfo: {}
108body:             |
109  bb.0:
110    liveins: $q0
111
112    ; CHECK-LABEL: name: test_v8f16.rint
113    ; CHECK: liveins: $q0
114    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
115    ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
116    ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1
117    ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2
118    ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3
119    ; CHECK: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4
120    ; CHECK: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5
121    ; CHECK: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6
122    ; CHECK: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7
123    ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
124    ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
125    ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
126    ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]]
127    ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
128    ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
129    ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]]
130    ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
131    ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
132    ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]]
133    ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
134    ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
135    ; CHECK: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_3]]
136    ; CHECK: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]]
137    ; CHECK: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]]
138    ; CHECK: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_4]]
139    ; CHECK: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]]
140    ; CHECK: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]]
141    ; CHECK: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_5]]
142    ; CHECK: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]]
143    ; CHECK: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]]
144    ; CHECK: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_6]]
145    ; CHECK: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]]
146    ; CHECK: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]]
147    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
148    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub
149    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
150    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub
151    ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
152    ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
153    ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub
154    ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
155    ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
156    ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub
157    ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
158    ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
159    ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub
160    ; CHECK: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
161    ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
162    ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub
163    ; CHECK: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
164    ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
165    ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub
166    ; CHECK: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
167    ; CHECK: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
168    ; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub
169    ; CHECK: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
170    ; CHECK: $q0 = COPY [[INSvi16lane6]]
171    ; CHECK: RET_ReallyLR implicit $q0
172    %0:fpr(<8 x s16>) = COPY $q0
173    %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
174    %32:fpr(s32) = G_FPEXT %2(s16)
175    %33:fpr(s32) = G_FRINT %32
176    %10:fpr(s16) = G_FPTRUNC %33(s32)
177    %30:fpr(s32) = G_FPEXT %3(s16)
178    %31:fpr(s32) = G_FRINT %30
179    %11:fpr(s16) = G_FPTRUNC %31(s32)
180    %28:fpr(s32) = G_FPEXT %4(s16)
181    %29:fpr(s32) = G_FRINT %28
182    %12:fpr(s16) = G_FPTRUNC %29(s32)
183    %26:fpr(s32) = G_FPEXT %5(s16)
184    %27:fpr(s32) = G_FRINT %26
185    %13:fpr(s16) = G_FPTRUNC %27(s32)
186    %24:fpr(s32) = G_FPEXT %6(s16)
187    %25:fpr(s32) = G_FRINT %24
188    %14:fpr(s16) = G_FPTRUNC %25(s32)
189    %22:fpr(s32) = G_FPEXT %7(s16)
190    %23:fpr(s32) = G_FRINT %22
191    %15:fpr(s16) = G_FPTRUNC %23(s32)
192    %20:fpr(s32) = G_FPEXT %8(s16)
193    %21:fpr(s32) = G_FRINT %20
194    %16:fpr(s16) = G_FPTRUNC %21(s32)
195    %18:fpr(s32) = G_FPEXT %9(s16)
196    %19:fpr(s32) = G_FRINT %18
197    %17:fpr(s16) = G_FPTRUNC %19(s32)
198    %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16)
199    $q0 = COPY %1(<8 x s16>)
200    RET_ReallyLR implicit $q0
201