1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
3---
4name:            v8s16_gpr
5alignment:       4
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $q1, $w0
12
13    ; CHECK-LABEL: name: v8s16_gpr
14    ; CHECK: liveins: $q1, $w0
15    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
16    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
17    ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
18    ; CHECK: $q0 = COPY [[INSvi16gpr]]
19    ; CHECK: RET_ReallyLR implicit $q0
20    %0:gpr(s32) = COPY $w0
21    %trunc:gpr(s16) = G_TRUNC %0
22    %1:fpr(<8 x s16>) = COPY $q1
23    %3:gpr(s32) = G_CONSTANT i32 1
24    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32)
25    $q0 = COPY %2(<8 x s16>)
26    RET_ReallyLR implicit $q0
27
28...
29---
30name:            v8s16_fpr
31alignment:       4
32legalized:       true
33regBankSelected: true
34tracksRegLiveness: true
35body:             |
36  bb.0:
37    liveins: $q1, $h0
38
39    ; CHECK-LABEL: name: v8s16_fpr
40    ; CHECK: liveins: $q1, $h0
41    ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
42    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
43    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
44    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
45    ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
46    ; CHECK: $q0 = COPY [[INSvi16lane]]
47    ; CHECK: RET_ReallyLR implicit $q0
48    %0:fpr(s16) = COPY $h0
49    %1:fpr(<8 x s16>) = COPY $q1
50    %3:gpr(s32) = G_CONSTANT i32 1
51    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
52    $q0 = COPY %2(<8 x s16>)
53    RET_ReallyLR implicit $q0
54
55...
56---
57name:            v4s32_fpr
58alignment:       4
59legalized:       true
60regBankSelected: true
61tracksRegLiveness: true
62body:             |
63  bb.0:
64    liveins: $q1, $s0
65
66    ; CHECK-LABEL: name: v4s32_fpr
67    ; CHECK: liveins: $q1, $s0
68    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
69    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
70    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
71    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
72    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
73    ; CHECK: $q0 = COPY [[INSvi32lane]]
74    ; CHECK: RET_ReallyLR implicit $q0
75    %0:fpr(s32) = COPY $s0
76    %1:fpr(<4 x s32>) = COPY $q1
77    %3:gpr(s32) = G_CONSTANT i32 1
78    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
79    $q0 = COPY %2(<4 x s32>)
80    RET_ReallyLR implicit $q0
81
82...
83---
84name:            v4s32_gpr
85alignment:       4
86legalized:       true
87regBankSelected: true
88tracksRegLiveness: true
89body:             |
90  bb.0:
91    liveins: $q0, $w0
92
93    ; CHECK-LABEL: name: v4s32_gpr
94    ; CHECK: liveins: $q0, $w0
95    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
96    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
97    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
98    ; CHECK: $q0 = COPY [[INSvi32gpr]]
99    ; CHECK: RET_ReallyLR implicit $q0
100    %0:gpr(s32) = COPY $w0
101    %1:fpr(<4 x s32>) = COPY $q0
102    %3:gpr(s32) = G_CONSTANT i32 1
103    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
104    $q0 = COPY %2(<4 x s32>)
105    RET_ReallyLR implicit $q0
106
107...
108---
109name:            v2s64_fpr
110alignment:       4
111legalized:       true
112regBankSelected: true
113tracksRegLiveness: true
114body:             |
115  bb.0:
116    liveins: $d0, $q1
117
118    ; CHECK-LABEL: name: v2s64_fpr
119    ; CHECK: liveins: $d0, $q1
120    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
121    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
122    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
123    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
124    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
125    ; CHECK: $q0 = COPY [[INSvi64lane]]
126    ; CHECK: RET_ReallyLR implicit $q0
127    %0:fpr(s64) = COPY $d0
128    %1:fpr(<2 x s64>) = COPY $q1
129    %3:gpr(s32) = G_CONSTANT i32 1
130    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
131    $q0 = COPY %2(<2 x s64>)
132    RET_ReallyLR implicit $q0
133
134...
135---
136name:            v2s64_gpr
137alignment:       4
138legalized:       true
139regBankSelected: true
140tracksRegLiveness: true
141body:             |
142  bb.0:
143    liveins: $q0, $x0
144
145    ; CHECK-LABEL: name: v2s64_gpr
146    ; CHECK: liveins: $q0, $x0
147    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
148    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
149    ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
150    ; CHECK: $q0 = COPY [[INSvi64gpr]]
151    ; CHECK: RET_ReallyLR implicit $q0
152    %0:gpr(s64) = COPY $x0
153    %1:fpr(<2 x s64>) = COPY $q0
154    %3:gpr(s32) = G_CONSTANT i32 0
155    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
156    $q0 = COPY %2(<2 x s64>)
157    RET_ReallyLR implicit $q0
158
159...
160---
161name:            v2s32_fpr
162alignment:       4
163legalized:       true
164regBankSelected: true
165tracksRegLiveness: true
166body:             |
167  bb.0:
168    liveins: $d1, $s0
169
170    ; CHECK-LABEL: name: v2s32_fpr
171    ; CHECK: liveins: $d1, $s0
172    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
173    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
174    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
175    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
176    ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
177    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
178    ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
179    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
180    ; CHECK: $d0 = COPY [[COPY2]]
181    ; CHECK: RET_ReallyLR implicit $d0
182    %0:fpr(s32) = COPY $s0
183    %1:fpr(<2 x s32>) = COPY $d1
184    %3:gpr(s32) = G_CONSTANT i32 1
185    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
186    $d0 = COPY %2(<2 x s32>)
187    RET_ReallyLR implicit $d0
188
189...
190---
191name:            v2s32_gpr
192alignment:       4
193legalized:       true
194regBankSelected: true
195tracksRegLiveness: true
196body:             |
197  bb.0:
198    liveins: $d0, $w0
199
200    ; CHECK-LABEL: name: v2s32_gpr
201    ; CHECK: liveins: $d0, $w0
202    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
203    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
204    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
205    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
206    ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
207    ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
208    ; CHECK: $d0 = COPY [[COPY2]]
209    ; CHECK: RET_ReallyLR implicit $d0
210    %0:gpr(s32) = COPY $w0
211    %1:fpr(<2 x s32>) = COPY $d0
212    %3:gpr(s32) = G_CONSTANT i32 1
213    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
214    $d0 = COPY %2(<2 x s32>)
215    RET_ReallyLR implicit $d0
216
217...
218