1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s 3--- | 4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 target triple = "aarch64" 6 7 define void @store_v2p0(<2 x i8*> %v, <2 x i8*>* %ptr) { 8 store <2 x i8*> %v, <2 x i8*>* %ptr 9 ret void 10 } 11 12 define <2 x i8*> @load_v2p0(<2 x i8*>* %ptr) { 13 %v = load <2 x i8*>, <2 x i8*>* %ptr 14 ret <2 x i8*> %v 15 } 16 17... 18--- 19name: store_v2p0 20alignment: 4 21legalized: true 22regBankSelected: true 23tracksRegLiveness: true 24registers: 25 - { id: 0, class: fpr } 26 - { id: 1, class: gpr } 27 - { id: 2, class: fpr } 28machineFunctionInfo: {} 29body: | 30 bb.1 (%ir-block.0): 31 liveins: $q0, $x0 32 33 ; CHECK-LABEL: name: store_v2p0 34 ; CHECK: liveins: $q0, $x0 35 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 36 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0 37 ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr) 38 ; CHECK: RET_ReallyLR 39 %0:fpr(<2 x p0>) = COPY $q0 40 %1:gpr(p0) = COPY $x0 41 %2:fpr(<2 x s64>) = G_BITCAST %0(<2 x p0>) 42 G_STORE %2(<2 x s64>), %1(p0) :: (store 16 into %ir.ptr) 43 RET_ReallyLR 44 45... 46--- 47name: load_v2p0 48alignment: 4 49legalized: true 50regBankSelected: true 51tracksRegLiveness: true 52registers: 53 - { id: 0, class: gpr } 54 - { id: 1, class: fpr } 55 - { id: 2, class: fpr } 56machineFunctionInfo: {} 57body: | 58 bb.1 (%ir-block.0): 59 liveins: $x0 60 61 ; CHECK-LABEL: name: load_v2p0 62 ; CHECK: liveins: $x0 63 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 64 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr) 65 ; CHECK: $q0 = COPY [[LDRQui]] 66 ; CHECK: RET_ReallyLR implicit $q0 67 %0:gpr(p0) = COPY $x0 68 %2:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) 69 %1:fpr(<2 x p0>) = G_BITCAST %2(<2 x s64>) 70 $q0 = COPY %1(<2 x p0>) 71 RET_ReallyLR implicit $q0 72 73... 74