1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 7 define void @load_s64_gpr(i64* %addr) { ret void } 8 define void @load_s32_gpr(i32* %addr) { ret void } 9 define void @load_s16_gpr_anyext(i16* %addr) { ret void } 10 define void @load_s16_gpr(i16* %addr) { ret void } 11 define void @load_s8_gpr_anyext(i8* %addr) { ret void } 12 define void @load_s8_gpr(i8* %addr) { ret void } 13 14 define void @load_fi_s64_gpr() { 15 %ptr0 = alloca i64 16 ret void 17 } 18 19 define void @load_gep_128_s64_gpr(i64* %addr) { ret void } 20 define void @load_gep_512_s32_gpr(i32* %addr) { ret void } 21 define void @load_gep_64_s16_gpr(i16* %addr) { ret void } 22 define void @load_gep_1_s8_gpr(i8* %addr) { ret void } 23 24 define void @load_s64_fpr(i64* %addr) { ret void } 25 define void @load_s32_fpr(i32* %addr) { ret void } 26 define void @load_s16_fpr(i16* %addr) { ret void } 27 define void @load_s8_fpr(i8* %addr) { ret void } 28 29 define void @load_gep_8_s64_fpr(i64* %addr) { ret void } 30 define void @load_gep_16_s32_fpr(i32* %addr) { ret void } 31 define void @load_gep_64_s16_fpr(i16* %addr) { ret void } 32 define void @load_gep_32_s8_fpr(i8* %addr) { ret void } 33 34 define void @load_v2s32(i64 *%addr) { ret void } 35 define void @load_v2s64(i64 *%addr) { ret void } 36 37 define void @load_4xi16(<4 x i16>* %ptr) { ret void } 38 define void @load_4xi32(<4 x i32>* %ptr) { ret void } 39 define void @load_8xi16(<8 x i16>* %ptr) { ret void } 40 define void @load_16xi8(<16 x i8>* %ptr) { ret void } 41 42... 43 44--- 45name: load_s64_gpr 46legalized: true 47regBankSelected: true 48 49registers: 50 - { id: 0, class: gpr } 51 - { id: 1, class: gpr } 52 53body: | 54 bb.0: 55 liveins: $x0 56 57 ; CHECK-LABEL: name: load_s64_gpr 58 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 59 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr) 60 ; CHECK: $x0 = COPY [[LDRXui]] 61 %0(p0) = COPY $x0 62 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) 63 $x0 = COPY %1(s64) 64... 65 66--- 67name: load_s32_gpr 68legalized: true 69regBankSelected: true 70 71registers: 72 - { id: 0, class: gpr } 73 - { id: 1, class: gpr } 74 75body: | 76 bb.0: 77 liveins: $x0 78 79 ; CHECK-LABEL: name: load_s32_gpr 80 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 81 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr) 82 ; CHECK: $w0 = COPY [[LDRWui]] 83 %0(p0) = COPY $x0 84 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) 85 $w0 = COPY %1(s32) 86... 87 88--- 89name: load_s16_gpr_anyext 90legalized: true 91regBankSelected: true 92 93body: | 94 bb.0: 95 liveins: $x0 96 97 ; CHECK-LABEL: name: load_s16_gpr_anyext 98 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 99 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) 100 ; CHECK: $w0 = COPY [[LDRHHui]] 101 %0:gpr(p0) = COPY $x0 102 %1:gpr(s32) = G_LOAD %0 :: (load 2 from %ir.addr) 103 $w0 = COPY %1(s32) 104... 105 106--- 107name: load_s16_gpr 108legalized: true 109regBankSelected: true 110 111registers: 112 - { id: 0, class: gpr } 113 - { id: 1, class: gpr } 114 115body: | 116 bb.0: 117 liveins: $x0 118 119 ; CHECK-LABEL: name: load_s16_gpr 120 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 121 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) 122 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] 123 ; CHECK: $w0 = COPY [[COPY1]] 124 %0(p0) = COPY $x0 125 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) 126 %2:gpr(s32) = G_ANYEXT %1 127 $w0 = COPY %2(s32) 128... 129 130--- 131name: load_s8_gpr_anyext 132legalized: true 133regBankSelected: true 134 135body: | 136 bb.0: 137 liveins: $x0 138 139 ; CHECK-LABEL: name: load_s8_gpr_anyext 140 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 141 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) 142 ; CHECK: $w0 = COPY [[LDRBBui]] 143 %0:gpr(p0) = COPY $x0 144 %1:gpr(s32) = G_LOAD %0 :: (load 1 from %ir.addr) 145 $w0 = COPY %1(s32) 146... 147 148--- 149name: load_s8_gpr 150legalized: true 151regBankSelected: true 152 153registers: 154 - { id: 0, class: gpr } 155 - { id: 1, class: gpr } 156 157body: | 158 bb.0: 159 liveins: $x0 160 161 ; CHECK-LABEL: name: load_s8_gpr 162 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 163 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) 164 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]] 165 ; CHECK: $w0 = COPY [[COPY1]] 166 %0(p0) = COPY $x0 167 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) 168 %2:gpr(s32) = G_ANYEXT %1 169 $w0 = COPY %2(s32) 170... 171 172--- 173name: load_fi_s64_gpr 174legalized: true 175regBankSelected: true 176 177registers: 178 - { id: 0, class: gpr } 179 - { id: 1, class: gpr } 180 181stack: 182 - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } 183 184body: | 185 bb.0: 186 liveins: $x0 187 188 ; CHECK-LABEL: name: load_fi_s64_gpr 189 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui %stack.0.ptr0, 0 :: (load 8) 190 ; CHECK: $x0 = COPY [[LDRXui]] 191 %0(p0) = G_FRAME_INDEX %stack.0.ptr0 192 %1(s64) = G_LOAD %0 :: (load 8) 193 $x0 = COPY %1(s64) 194... 195 196--- 197name: load_gep_128_s64_gpr 198legalized: true 199regBankSelected: true 200 201registers: 202 - { id: 0, class: gpr } 203 - { id: 1, class: gpr } 204 - { id: 2, class: gpr } 205 - { id: 3, class: gpr } 206 207body: | 208 bb.0: 209 liveins: $x0 210 211 ; CHECK-LABEL: name: load_gep_128_s64_gpr 212 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 213 ; CHECK: [[LDRXui:%[0-9]+]]:gpr64 = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr) 214 ; CHECK: $x0 = COPY [[LDRXui]] 215 %0(p0) = COPY $x0 216 %1(s64) = G_CONSTANT i64 128 217 %2(p0) = G_PTR_ADD %0, %1 218 %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) 219 $x0 = COPY %3 220... 221 222--- 223name: load_gep_512_s32_gpr 224legalized: true 225regBankSelected: true 226 227registers: 228 - { id: 0, class: gpr } 229 - { id: 1, class: gpr } 230 - { id: 2, class: gpr } 231 - { id: 3, class: gpr } 232 233body: | 234 bb.0: 235 liveins: $x0 236 237 ; CHECK-LABEL: name: load_gep_512_s32_gpr 238 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 239 ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr) 240 ; CHECK: $w0 = COPY [[LDRWui]] 241 %0(p0) = COPY $x0 242 %1(s64) = G_CONSTANT i64 512 243 %2(p0) = G_PTR_ADD %0, %1 244 %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) 245 $w0 = COPY %3 246... 247 248--- 249name: load_gep_64_s16_gpr 250legalized: true 251regBankSelected: true 252 253registers: 254 - { id: 0, class: gpr } 255 - { id: 1, class: gpr } 256 - { id: 2, class: gpr } 257 - { id: 3, class: gpr } 258 259body: | 260 bb.0: 261 liveins: $x0 262 263 ; CHECK-LABEL: name: load_gep_64_s16_gpr 264 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 265 ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr) 266 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]] 267 ; CHECK: $w0 = COPY [[COPY1]] 268 %0(p0) = COPY $x0 269 %1(s64) = G_CONSTANT i64 64 270 %2(p0) = G_PTR_ADD %0, %1 271 %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) 272 %4:gpr(s32) = G_ANYEXT %3 273 $w0 = COPY %4 274... 275 276--- 277name: load_gep_1_s8_gpr 278legalized: true 279regBankSelected: true 280 281registers: 282 - { id: 0, class: gpr } 283 - { id: 1, class: gpr } 284 - { id: 2, class: gpr } 285 - { id: 3, class: gpr } 286 287body: | 288 bb.0: 289 liveins: $x0 290 291 ; CHECK-LABEL: name: load_gep_1_s8_gpr 292 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 293 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr) 294 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]] 295 ; CHECK: $w0 = COPY [[COPY1]] 296 %0(p0) = COPY $x0 297 %1(s64) = G_CONSTANT i64 1 298 %2(p0) = G_PTR_ADD %0, %1 299 %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) 300 %4:gpr(s32) = G_ANYEXT %3 301 $w0 = COPY %4 302... 303 304--- 305name: load_s64_fpr 306legalized: true 307regBankSelected: true 308 309registers: 310 - { id: 0, class: gpr } 311 - { id: 1, class: fpr } 312 313body: | 314 bb.0: 315 liveins: $x0 316 317 ; CHECK-LABEL: name: load_s64_fpr 318 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 319 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) 320 ; CHECK: $d0 = COPY [[LDRDui]] 321 %0(p0) = COPY $x0 322 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) 323 $d0 = COPY %1(s64) 324... 325 326--- 327name: load_s32_fpr 328legalized: true 329regBankSelected: true 330 331registers: 332 - { id: 0, class: gpr } 333 - { id: 1, class: fpr } 334 335body: | 336 bb.0: 337 liveins: $x0 338 339 ; CHECK-LABEL: name: load_s32_fpr 340 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 341 ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr) 342 ; CHECK: $s0 = COPY [[LDRSui]] 343 %0(p0) = COPY $x0 344 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) 345 $s0 = COPY %1(s32) 346... 347 348--- 349name: load_s16_fpr 350legalized: true 351regBankSelected: true 352 353registers: 354 - { id: 0, class: gpr } 355 - { id: 1, class: fpr } 356 357body: | 358 bb.0: 359 liveins: $x0 360 361 ; CHECK-LABEL: name: load_s16_fpr 362 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 363 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr) 364 ; CHECK: $h0 = COPY [[LDRHui]] 365 %0(p0) = COPY $x0 366 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) 367 $h0 = COPY %1(s16) 368... 369 370--- 371name: load_s8_fpr 372legalized: true 373regBankSelected: true 374 375registers: 376 - { id: 0, class: gpr } 377 - { id: 1, class: fpr } 378 379body: | 380 bb.0: 381 liveins: $x0 382 383 ; CHECK-LABEL: name: load_s8_fpr 384 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 385 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr) 386 ; CHECK: $b0 = COPY [[LDRBui]] 387 %0(p0) = COPY $x0 388 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) 389 $b0 = COPY %1(s8) 390... 391 392--- 393name: load_gep_8_s64_fpr 394legalized: true 395regBankSelected: true 396 397registers: 398 - { id: 0, class: gpr } 399 - { id: 1, class: gpr } 400 - { id: 2, class: gpr } 401 - { id: 3, class: fpr } 402 403body: | 404 bb.0: 405 liveins: $x0 406 407 ; CHECK-LABEL: name: load_gep_8_s64_fpr 408 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 409 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr) 410 ; CHECK: $d0 = COPY [[LDRDui]] 411 %0(p0) = COPY $x0 412 %1(s64) = G_CONSTANT i64 8 413 %2(p0) = G_PTR_ADD %0, %1 414 %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) 415 $d0 = COPY %3 416... 417 418--- 419name: load_gep_16_s32_fpr 420legalized: true 421regBankSelected: true 422 423registers: 424 - { id: 0, class: gpr } 425 - { id: 1, class: gpr } 426 - { id: 2, class: gpr } 427 - { id: 3, class: fpr } 428 429body: | 430 bb.0: 431 liveins: $x0 432 433 ; CHECK-LABEL: name: load_gep_16_s32_fpr 434 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 435 ; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr) 436 ; CHECK: $s0 = COPY [[LDRSui]] 437 %0(p0) = COPY $x0 438 %1(s64) = G_CONSTANT i64 16 439 %2(p0) = G_PTR_ADD %0, %1 440 %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) 441 $s0 = COPY %3 442... 443 444--- 445name: load_gep_64_s16_fpr 446legalized: true 447regBankSelected: true 448 449registers: 450 - { id: 0, class: gpr } 451 - { id: 1, class: gpr } 452 - { id: 2, class: gpr } 453 - { id: 3, class: fpr } 454 455body: | 456 bb.0: 457 liveins: $x0 458 459 ; CHECK-LABEL: name: load_gep_64_s16_fpr 460 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 461 ; CHECK: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr) 462 ; CHECK: $h0 = COPY [[LDRHui]] 463 %0(p0) = COPY $x0 464 %1(s64) = G_CONSTANT i64 64 465 %2(p0) = G_PTR_ADD %0, %1 466 %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) 467 $h0 = COPY %3 468... 469 470--- 471name: load_gep_32_s8_fpr 472legalized: true 473regBankSelected: true 474 475registers: 476 - { id: 0, class: gpr } 477 - { id: 1, class: gpr } 478 - { id: 2, class: gpr } 479 - { id: 3, class: fpr } 480 481body: | 482 bb.0: 483 liveins: $x0 484 485 ; CHECK-LABEL: name: load_gep_32_s8_fpr 486 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 487 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr) 488 ; CHECK: $b0 = COPY [[LDRBui]] 489 %0(p0) = COPY $x0 490 %1(s64) = G_CONSTANT i64 32 491 %2(p0) = G_PTR_ADD %0, %1 492 %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) 493 $b0 = COPY %3 494... 495--- 496name: load_v2s32 497legalized: true 498regBankSelected: true 499 500registers: 501 - { id: 0, class: gpr } 502 - { id: 1, class: fpr } 503 504body: | 505 bb.0: 506 liveins: $x0 507 508 ; CHECK-LABEL: name: load_v2s32 509 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 510 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) 511 ; CHECK: $d0 = COPY [[LDRDui]] 512 %0(p0) = COPY $x0 513 %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr) 514 $d0 = COPY %1(<2 x s32>) 515... 516--- 517name: load_v2s64 518legalized: true 519regBankSelected: true 520 521registers: 522 - { id: 0, class: gpr } 523 - { id: 1, class: fpr } 524 525body: | 526 bb.0: 527 liveins: $x0 528 529 ; CHECK-LABEL: name: load_v2s64 530 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 531 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.addr) 532 ; CHECK: $q0 = COPY [[LDRQui]] 533 %0(p0) = COPY $x0 534 %1(<2 x s64>) = G_LOAD %0 :: (load 16 from %ir.addr) 535 $q0 = COPY %1(<2 x s64>) 536... 537--- 538name: load_4xi16 539alignment: 4 540legalized: true 541regBankSelected: true 542tracksRegLiveness: true 543registers: 544 - { id: 0, class: gpr } 545 - { id: 1, class: fpr } 546machineFunctionInfo: {} 547body: | 548 bb.1 (%ir-block.0): 549 liveins: $x0 550 551 ; CHECK-LABEL: name: load_4xi16 552 ; CHECK: liveins: $x0 553 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 554 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load 8 from %ir.ptr) 555 ; CHECK: $d0 = COPY [[LDRDui]] 556 ; CHECK: RET_ReallyLR implicit $d0 557 %0:gpr(p0) = COPY $x0 558 %1:fpr(<4 x s16>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr) 559 $d0 = COPY %1(<4 x s16>) 560 RET_ReallyLR implicit $d0 561 562... 563--- 564name: load_4xi32 565alignment: 4 566legalized: true 567regBankSelected: true 568tracksRegLiveness: true 569registers: 570 - { id: 0, class: gpr } 571 - { id: 1, class: fpr } 572machineFunctionInfo: {} 573body: | 574 bb.1 (%ir-block.0): 575 liveins: $x0 576 577 ; CHECK-LABEL: name: load_4xi32 578 ; CHECK: liveins: $x0 579 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 580 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr) 581 ; CHECK: $q0 = COPY [[LDRQui]] 582 ; CHECK: RET_ReallyLR implicit $q0 583 %0:gpr(p0) = COPY $x0 584 %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) 585 $q0 = COPY %1(<4 x s32>) 586 RET_ReallyLR implicit $q0 587 588... 589--- 590name: load_8xi16 591alignment: 4 592legalized: true 593regBankSelected: true 594tracksRegLiveness: true 595registers: 596 - { id: 0, class: gpr } 597 - { id: 1, class: fpr } 598machineFunctionInfo: {} 599body: | 600 bb.1 (%ir-block.0): 601 liveins: $x0 602 603 ; CHECK-LABEL: name: load_8xi16 604 ; CHECK: liveins: $x0 605 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 606 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr) 607 ; CHECK: $q0 = COPY [[LDRQui]] 608 ; CHECK: RET_ReallyLR implicit $q0 609 %0:gpr(p0) = COPY $x0 610 %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) 611 $q0 = COPY %1(<8 x s16>) 612 RET_ReallyLR implicit $q0 613 614... 615--- 616name: load_16xi8 617alignment: 4 618legalized: true 619regBankSelected: true 620tracksRegLiveness: true 621registers: 622 - { id: 0, class: gpr } 623 - { id: 1, class: fpr } 624machineFunctionInfo: {} 625body: | 626 bb.1 (%ir-block.0): 627 liveins: $x0 628 629 ; CHECK-LABEL: name: load_16xi8 630 ; CHECK: liveins: $x0 631 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 632 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr) 633 ; CHECK: $q0 = COPY [[LDRQui]] 634 ; CHECK: RET_ReallyLR implicit $q0 635 %0:gpr(p0) = COPY $x0 636 %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) 637 $q0 = COPY %1(<16 x s8>) 638 RET_ReallyLR implicit $q0 639 640... 641