1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6
7  define void @vcvtfxu2fp_s64_fpr() { ret void }
8...
9
10---
11# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
12name:            vcvtfxu2fp_s64_fpr
13legalized:       true
14regBankSelected: true
15
16registers:
17  - { id: 0, class: fpr }
18  - { id: 1, class: gpr }
19  - { id: 2, class: fpr }
20
21body:             |
22  bb.0:
23    liveins: $d0
24
25    ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
26    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
27    ; CHECK: [[UCVTFd:%[0-9]+]]:fpr64 = UCVTFd [[COPY]], 12
28    ; CHECK: $d1 = COPY [[UCVTFd]]
29    %0(s64) = COPY $d0
30    %1(s32) = G_CONSTANT i32 12
31    %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
32    $d1 = COPY %2(s64)
33...
34