1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
3---
4name:            redundant_zext_8
5legalized:       true
6regBankSelected: true
7tracksRegLiveness: true
8body:             |
9  bb.1:
10    liveins: $x0
11
12    ; CHECK-LABEL: name: redundant_zext_8
13    ; CHECK: liveins: $x0
14    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
15    ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1)
16    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
17    ; CHECK: $w0 = COPY [[COPY1]]
18    ; CHECK: RET_ReallyLR implicit $w0
19    %1:gpr(p0) = COPY $x0
20    %2:gpr(s8) = G_LOAD %1(p0) :: (load 1)
21    %3:gpr(s32) = G_ZEXT %2(s8)
22    $w0 = COPY %3(s32)
23    RET_ReallyLR implicit $w0
24
25...
26---
27name:            redundant_zext_16
28legalized:       true
29regBankSelected: true
30tracksRegLiveness: true
31body:             |
32  bb.1:
33    liveins: $x0
34
35    ; CHECK-LABEL: name: redundant_zext_16
36    ; CHECK: liveins: $x0
37    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
38    ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2)
39    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
40    ; CHECK: $w0 = COPY [[COPY1]]
41    ; CHECK: RET_ReallyLR implicit $w0
42    %1:gpr(p0) = COPY $x0
43    %2:gpr(s16) = G_LOAD %1(p0) :: (load 2)
44    %3:gpr(s32) = G_ZEXT %2(s16)
45    $w0 = COPY %3(s32)
46    RET_ReallyLR implicit $w0
47
48...
49