1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Test selecting G_REV instructions.
5#
6# Each test is named like:
7#
8# (G_REV_VERSION)_(INSTRUCTION_PRODUCED)
9#
10# Each of these patterns come from AArch64GenGlobalISel.inc.
11#
12
13...
14---
15name:            rev64_REV64v2i32
16alignment:       4
17legalized:       true
18regBankSelected: true
19tracksRegLiveness: true
20body:             |
21  bb.0.entry:
22    liveins: $d0
23    ; CHECK-LABEL: name: rev64_REV64v2i32
24    ; CHECK: liveins: $d0
25    ; CHECK: %copy:fpr64 = COPY $d0
26    ; CHECK: %rev:fpr64 = REV64v2i32 %copy
27    ; CHECK: $d0 = COPY %rev
28    ; CHECK: RET_ReallyLR implicit $d0
29    %copy:fpr(<2 x s32>) = COPY $d0
30    %rev:fpr(<2 x s32>) = G_REV64 %copy
31    $d0 = COPY %rev(<2 x s32>)
32    RET_ReallyLR implicit $d0
33
34...
35---
36name:            rev64_REV64v4i16
37alignment:       4
38legalized:       true
39regBankSelected: true
40tracksRegLiveness: true
41body:             |
42  bb.0.entry:
43    liveins: $d0
44    ; CHECK-LABEL: name: rev64_REV64v4i16
45    ; CHECK: liveins: $d0
46    ; CHECK: %copy:fpr64 = COPY $d0
47    ; CHECK: %rev:fpr64 = REV64v4i16 %copy
48    ; CHECK: $d0 = COPY %rev
49    ; CHECK: RET_ReallyLR implicit $d0
50    %copy:fpr(<4 x s16>) = COPY $d0
51    %rev:fpr(<4 x s16>) = G_REV64 %copy
52    $d0 = COPY %rev(<4 x s16>)
53    RET_ReallyLR implicit $d0
54
55...
56---
57name:            rev64_REV64v4i32
58alignment:       4
59legalized:       true
60regBankSelected: true
61tracksRegLiveness: true
62body:             |
63  bb.0.entry:
64    liveins: $q0
65    ; CHECK-LABEL: name: rev64_REV64v4i32
66    ; CHECK: liveins: $q0
67    ; CHECK: %copy:fpr128 = COPY $q0
68    ; CHECK: %rev:fpr128 = REV64v4i32 %copy
69    ; CHECK: $q0 = COPY %rev
70    ; CHECK: RET_ReallyLR implicit $q0
71    %copy:fpr(<4 x s32>) = COPY $q0
72    %rev:fpr(<4 x s32>) = G_REV64 %copy
73    $q0 = COPY %rev(<4 x s32>)
74    RET_ReallyLR implicit $q0
75
76...
77---
78name:            rev64_REV64v8i8
79alignment:       4
80legalized:       true
81regBankSelected: true
82tracksRegLiveness: true
83body:             |
84  bb.0.entry:
85    liveins: $q0
86    ; CHECK-LABEL: name: rev64_REV64v8i8
87    ; CHECK: liveins: $q0
88    ; CHECK: %copy:fpr64 = COPY $d0
89    ; CHECK: %rev:fpr64 = REV64v8i8 %copy
90    ; CHECK: $d0 = COPY %rev
91    ; CHECK: RET_ReallyLR implicit $d0
92    %copy:fpr(<8 x s8>) = COPY $d0
93    %rev:fpr(<8 x s8>) = G_REV64 %copy
94    $d0 = COPY %rev(<8 x s8>)
95    RET_ReallyLR implicit $d0
96
97...
98---
99name:            rev64_REV64v8i16
100alignment:       4
101legalized:       true
102regBankSelected: true
103tracksRegLiveness: true
104body:             |
105  bb.0.entry:
106    liveins: $q0
107    ; CHECK-LABEL: name: rev64_REV64v8i16
108    ; CHECK: liveins: $q0
109    ; CHECK: %copy:fpr128 = COPY $q0
110    ; CHECK: %rev:fpr128 = REV64v8i16 %copy
111    ; CHECK: $q0 = COPY %rev
112    ; CHECK: RET_ReallyLR implicit $q0
113    %copy:fpr(<8 x s16>) = COPY $q0
114    %rev:fpr(<8 x s16>) = G_REV64 %copy
115    $q0 = COPY %rev(<8 x s16>)
116    RET_ReallyLR implicit $q0
117
118...
119---
120name:            rev64_REV64v16i8
121alignment:       4
122legalized:       true
123regBankSelected: true
124tracksRegLiveness: true
125body:             |
126  bb.0.entry:
127    liveins: $q0
128    ; CHECK-LABEL: name: rev64_REV64v16i8
129    ; CHECK: liveins: $q0
130    ; CHECK: %copy:fpr128 = COPY $q0
131    ; CHECK: %rev:fpr128 = REV64v16i8 %copy
132    ; CHECK: $q0 = COPY %rev
133    ; CHECK: RET_ReallyLR implicit $q0
134    %copy:fpr(<16 x s8>) = COPY $q0
135    %rev:fpr(<16 x s8>) = G_REV64 %copy
136    $q0 = COPY %rev(<16 x s8>)
137    RET_ReallyLR implicit $q0
138
139...
140---
141name:            rev32_REV32v4i16
142alignment:       4
143legalized:       true
144regBankSelected: true
145tracksRegLiveness: true
146body:             |
147  bb.0.entry:
148    liveins: $d0
149    ; CHECK-LABEL: name: rev32_REV32v4i16
150    ; CHECK: liveins: $d0
151    ; CHECK: %copy:fpr64 = COPY $d0
152    ; CHECK: %rev:fpr64 = REV32v4i16 %copy
153    ; CHECK: $d0 = COPY %rev
154    ; CHECK: RET_ReallyLR implicit $d0
155    %copy:fpr(<4 x s16>) = COPY $d0
156    %rev:fpr(<4 x s16>) = G_REV32 %copy
157    $d0 = COPY %rev(<4 x s16>)
158    RET_ReallyLR implicit $d0
159
160...
161---
162name:            rev32_REV32v8i8
163alignment:       4
164legalized:       true
165regBankSelected: true
166tracksRegLiveness: true
167body:             |
168  bb.0.entry:
169    liveins: $d0
170    ; CHECK-LABEL: name: rev32_REV32v8i8
171    ; CHECK: liveins: $d0
172    ; CHECK: %copy:fpr64 = COPY $d0
173    ; CHECK: %rev:fpr64 = REV32v8i8 %copy
174    ; CHECK: $d0 = COPY %rev
175    ; CHECK: RET_ReallyLR implicit $d0
176    %copy:fpr(<8 x s8>) = COPY $d0
177    %rev:fpr(<8 x s8>) = G_REV32 %copy
178    $d0 = COPY %rev(<8 x s8>)
179    RET_ReallyLR implicit $d0
180
181...
182---
183name:            rev32_REV32v8i16
184alignment:       4
185legalized:       true
186regBankSelected: true
187tracksRegLiveness: true
188body:             |
189  bb.0.entry:
190    liveins: $q0
191    ; CHECK-LABEL: name: rev32_REV32v8i16
192    ; CHECK: liveins: $q0
193    ; CHECK: %copy:fpr128 = COPY $q0
194    ; CHECK: %rev:fpr128 = REV32v8i16 %copy
195    ; CHECK: $q0 = COPY %rev
196    ; CHECK: RET_ReallyLR implicit $q0
197    %copy:fpr(<8 x s16>) = COPY $q0
198    %rev:fpr(<8 x s16>) = G_REV32 %copy
199    $q0 = COPY %rev(<8 x s16>)
200    RET_ReallyLR implicit $q0
201
202...
203---
204name:            rev32_REV32v16i8
205alignment:       4
206legalized:       true
207regBankSelected: true
208tracksRegLiveness: true
209body:             |
210  bb.0.entry:
211    liveins: $q0
212    ; CHECK-LABEL: name: rev32_REV32v16i8
213    ; CHECK: liveins: $q0
214    ; CHECK: %copy:fpr128 = COPY $q0
215    ; CHECK: %rev:fpr128 = REV32v16i8 %copy
216    ; CHECK: $q0 = COPY %rev
217    ; CHECK: RET_ReallyLR implicit $q0
218    %copy:fpr(<16 x s8>) = COPY $q0
219    %rev:fpr(<16 x s8>) = G_REV32 %copy
220    $q0 = COPY %rev(<16 x s8>)
221    RET_ReallyLR implicit $q0
222
223...
224---
225name:            rev16_REV16v8i8
226alignment:       4
227legalized:       true
228regBankSelected: true
229tracksRegLiveness: true
230body:             |
231  bb.0.entry:
232    liveins: $q0
233    ; CHECK-LABEL: name: rev16_REV16v8i8
234    ; CHECK: liveins: $q0
235    ; CHECK: %copy:fpr64 = COPY $d0
236    ; CHECK: %rev:fpr64 = REV16v8i8 %copy
237    ; CHECK: $d0 = COPY %rev
238    ; CHECK: RET_ReallyLR implicit $d0
239    %copy:fpr(<8 x s8>) = COPY $d0
240    %rev:fpr(<8 x s8>) = G_REV16 %copy
241    $d0 = COPY %rev(<8 x s8>)
242    RET_ReallyLR implicit $d0
243
244...
245---
246name:            rev16_REV16v16i8
247alignment:       4
248legalized:       true
249regBankSelected: true
250tracksRegLiveness: true
251body:             |
252  bb.0.entry:
253    liveins: $q0
254    ; CHECK-LABEL: name: rev16_REV16v16i8
255    ; CHECK: liveins: $q0
256    ; CHECK: %copy:fpr128 = COPY $q0
257    ; CHECK: %rev:fpr128 = REV16v16i8 %copy
258    ; CHECK: $q0 = COPY %rev
259    ; CHECK: RET_ReallyLR implicit $q0
260    %copy:fpr(<16 x s8>) = COPY $q0
261    %rev:fpr(<16 x s8>) = G_REV16 %copy
262    $q0 = COPY %rev(<16 x s8>)
263    RET_ReallyLR implicit $q0
264