1
2# RUN: llc -O0 -mattr=-fullfp16 -mtriple=aarch64-- \
3# RUN: -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
4
5--- |
6  define <2 x double> @test_v2s64_unmerge(<2 x double> %a) {
7    ret <2 x double> %a
8  }
9
10  define <4 x float> @test_v4s32_unmerge(<4 x float> %a) {
11    ret <4 x float> %a
12  }
13
14  define <4 x half> @test_v4s16_unmerge(<4 x half> %a) {
15    ret <4 x half> %a
16  }
17
18  define <8 x half> @test_v8s16_unmerge(<8 x half> %a) {
19    ret <8 x half> %a
20  }
21
22  define <2 x float> @test_vecsplit_2v2s32_v4s32(<4 x float> %a) {
23    ret <2 x float> undef
24  }
25
26  define <2 x half> @test_vecsplit_2v2s16_v4s16(<4 x half> %a) {
27    ret <2 x half> undef
28  }
29
30  define void @test_s128(i128 %p) { ret void }
31
32...
33---
34name:            test_v2s64_unmerge
35alignment:       4
36legalized:       true
37regBankSelected: true
38tracksRegLiveness: true
39registers:
40  - { id: 0, class: fpr }
41  - { id: 1, class: fpr }
42  - { id: 2, class: fpr }
43  - { id: 3, class: fpr }
44body:             |
45  bb.1 (%ir-block.0):
46    liveins: $q0
47    ; CHECK-LABEL: name:            test_v2s64_unmerge
48    %0:fpr(<2 x s64>) = COPY $q0
49
50    ; Since 2 * 64 = 128, we can just directly copy.
51    ; CHECK: %2:fpr64 = COPY %0.dsub
52    ; CHECK: %3:fpr64 = CPYi64 %0, 1
53    %2:fpr(s64), %3:fpr(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
54
55    %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
56    $q0 = COPY %1(<2 x s64>)
57    RET_ReallyLR implicit $q0
58...
59---
60name:            test_v4s32_unmerge
61alignment:       4
62legalized:       true
63regBankSelected: true
64tracksRegLiveness: true
65registers:
66  - { id: 0, class: fpr }
67  - { id: 1, class: fpr }
68  - { id: 2, class: fpr }
69  - { id: 3, class: fpr }
70  - { id: 4, class: fpr }
71  - { id: 5, class: fpr }
72body:             |
73  bb.1 (%ir-block.0):
74    liveins: $q0
75    ; CHECK-LABEL: name:            test_v4s32_unmerge
76    %0:fpr(<4 x s32>) = COPY $q0
77
78    ; Since 4 * 32 = 128, we can just directly copy.
79    ; CHECK: %2:fpr32 = COPY %0.ssub
80    ; CHECK: %3:fpr32 = CPYi32 %0, 1
81    ; CHECK: %4:fpr32 = CPYi32 %0, 2
82    ; CHECK: %5:fpr32 = CPYi32 %0, 3
83    %2:fpr(s32), %3:fpr(s32), %4:fpr(s32), %5:fpr(s32) = G_UNMERGE_VALUES %0(<4 x s32>)
84
85    %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %4(s32), %5(s32)
86    $q0 = COPY %1(<4 x s32>)
87    RET_ReallyLR implicit $q0
88...
89---
90name:            test_v4s16_unmerge
91alignment:       4
92legalized:       true
93regBankSelected: true
94tracksRegLiveness: true
95registers:
96  - { id: 0, class: fpr }
97  - { id: 1, class: fpr }
98  - { id: 2, class: fpr }
99  - { id: 3, class: fpr }
100  - { id: 4, class: fpr }
101  - { id: 5, class: fpr }
102body:             |
103  bb.1 (%ir-block.0):
104    liveins: $d0
105    ; CHECK-LABEL: name:            test_v4s16_unmerge
106    %0:fpr(<4 x s16>) = COPY $d0
107
108    ; Since 4 * 16 != 128, we need to widen using implicit defs.
109    ; Note that we expect to reuse one of the INSERT_SUBREG results, as CPYi16
110    ; expects a lane > 0.
111    ; CHECK-DAG: [[IMPDEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
112    ; CHECK-NEXT: [[INS_SHARED:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF1]], %0, %subreg.dsub
113    ; CHECK: [[IMPDEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
114    ; CHECK-NEXT: [[INS2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF2]], %0, %subreg.dsub
115    ; CHECK: [[IMPDEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
116    ; CHECK-NEXT: [[INS3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[IMPDEF3]], %0, %subreg.dsub
117    ; CHECK: %2:fpr16 = COPY [[INS_SHARED]].hsub
118    ; CHECK: %3:fpr16 = CPYi16 [[INS_SHARED]], 1
119    ; CHECK: %4:fpr16 = CPYi16 [[INS2]], 2
120    ; CHECK: %5:fpr16 = CPYi16 [[INS3]], 3
121    %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
122
123    %1:fpr(<4 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16), %4(s16), %5(s16)
124    $d0 = COPY %1(<4 x s16>)
125    RET_ReallyLR implicit $d0
126...
127---
128name:            test_v8s16_unmerge
129alignment:       4
130legalized:       true
131regBankSelected: true
132tracksRegLiveness: true
133registers:
134  - { id: 0, class: fpr }
135  - { id: 1, class: fpr }
136  - { id: 2, class: fpr }
137  - { id: 3, class: fpr }
138  - { id: 4, class: fpr }
139  - { id: 5, class: fpr }
140  - { id: 6, class: fpr }
141  - { id: 7, class: fpr }
142  - { id: 8, class: fpr }
143  - { id: 9, class: fpr }
144body:             |
145  bb.1 (%ir-block.0):
146    liveins: $q0
147    ; CHECK-LABEL: name:            test_v8s16_unmerge
148    %0:fpr(<8 x s16>) = COPY $q0
149
150    ; Since 8 * 16 = 128, we can just directly copy.
151    ; CHECK: %2:fpr16 = COPY %0.hsub
152    ; CHECK: %3:fpr16 = CPYi16 %0, 1
153    ; CHECK: %4:fpr16 = CPYi16 %0, 2
154    ; CHECK: %5:fpr16 = CPYi16 %0, 3
155    ; CHECK: %6:fpr16 = CPYi16 %0, 4
156    ; CHECK: %7:fpr16 = CPYi16 %0, 5
157    ; CHECK: %8:fpr16 = CPYi16 %0, 6
158    ; CHECK: %9:fpr16 = CPYi16 %0, 7
159    %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>)
160
161    %1:fpr(<8 x s16>) = G_BUILD_VECTOR %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16)
162    $q0 = COPY %1(<8 x s16>)
163    RET_ReallyLR implicit $q0
164...
165---
166name:            test_vecsplit_2v2s32_v4s32
167alignment:       4
168legalized:       true
169regBankSelected: true
170tracksRegLiveness: true
171body:             |
172  bb.1 (%ir-block.0):
173    liveins: $q0
174    ; CHECK-LABEL: name: test_vecsplit_2v2s32_v4s32
175    ; CHECK: liveins: $q0
176    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
177    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
178    ; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1
179    ; CHECK: $d0 = COPY [[COPY1]]
180    ; CHECK: $d1 = COPY [[CPYi64_]]
181    ; CHECK: RET_ReallyLR implicit $d0
182    %0:fpr(<4 x s32>) = COPY $q0
183    %1:fpr(<2 x s32>), %2:fpr(<2 x s32>) = G_UNMERGE_VALUES %0(<4 x s32>)
184    $d0 = COPY %1(<2 x s32>)
185    $d1 = COPY %2(<2 x s32>)
186    RET_ReallyLR implicit $d0
187...
188---
189name:            test_vecsplit_2v2s16_v4s16
190alignment:       4
191legalized:       true
192regBankSelected: true
193tracksRegLiveness: true
194body:             |
195  bb.1 (%ir-block.0):
196    liveins: $d0
197    ; CHECK-LABEL: name: test_vecsplit_2v2s16_v4s16
198    ; CHECK: liveins: $d0
199    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
200    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
201    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
202    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
203    ; CHECK: [[CPYi32_:%[0-9]+]]:fpr32 = CPYi32 [[INSERT_SUBREG]], 1
204    ; CHECK: $s0 = COPY [[COPY1]]
205    ; CHECK: $s1 = COPY [[CPYi32_]]
206    ; CHECK: RET_ReallyLR implicit $s0
207    %0:fpr(<4 x s16>) = COPY $d0
208    %1:fpr(<2 x s16>), %2:fpr(<2 x s16>) = G_UNMERGE_VALUES %0(<4 x s16>)
209    $s0 = COPY %1(<2 x s16>)
210    $s1 = COPY %2(<2 x s16>)
211    RET_ReallyLR implicit $s0
212...
213---
214name:            test_s128
215alignment:       4
216legalized:       true
217regBankSelected: true
218tracksRegLiveness: true
219body:             |
220  bb.1:
221    liveins: $q0
222    %0:fpr(s128) = COPY $q0
223    %1:fpr(s64), %2:fpr(s64) = G_UNMERGE_VALUES %0(s128)
224    $d0 = COPY %1(s64)
225    $d1 = COPY %2(s64)
226    RET_ReallyLR implicit $d0, implicit $d1
227...
228