1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2#
3# Check that we can select G_UZP1 and G_UZP2 via the tablegen importer.
4#
5# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
6
7...
8---
9name:            uzp1_v4s32
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13body:             |
14  bb.1.entry:
15    liveins: $q0, $q1
16
17    ; CHECK-LABEL: name: uzp1_v4s32
18    ; CHECK: liveins: $q0, $q1
19    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
20    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
21    ; CHECK: [[UZP1v4i32_:%[0-9]+]]:fpr128 = UZP1v4i32 [[COPY]], [[COPY1]]
22    ; CHECK: $q0 = COPY [[UZP1v4i32_]]
23    ; CHECK: RET_ReallyLR implicit $q0
24    %0:fpr(<4 x s32>) = COPY $q0
25    %1:fpr(<4 x s32>) = COPY $q1
26    %2:fpr(<4 x s32>) = G_UZP1 %0, %1
27    $q0 = COPY %2(<4 x s32>)
28    RET_ReallyLR implicit $q0
29
30...
31---
32name:            uzp2_v4s32
33legalized:       true
34regBankSelected: true
35tracksRegLiveness: true
36body:             |
37  bb.1.entry:
38  liveins: $q0, $q1
39
40    ; CHECK-LABEL: name: uzp2_v4s32
41    ; CHECK: liveins: $q0, $q1
42    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
43    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
44    ; CHECK: [[UZP2v4i32_:%[0-9]+]]:fpr128 = UZP2v4i32 [[COPY]], [[COPY1]]
45    ; CHECK: $q0 = COPY [[UZP2v4i32_]]
46    ; CHECK: RET_ReallyLR implicit $q0
47  %0:fpr(<4 x s32>) = COPY $q0
48  %1:fpr(<4 x s32>) = COPY $q1
49  %2:fpr(<4 x s32>) = G_UZP2 %0, %1
50  $q0 = COPY %2(<4 x s32>)
51  RET_ReallyLR implicit $q0
52
53...
54