1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4; 5; SDIV 6; 7 8define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 9; CHECK-LABEL: sdiv_i8: 10; CHECK: // %bb.0: 11; CHECK-NEXT: sunpkhi z2.h, z1.b 12; CHECK-NEXT: sunpkhi z3.h, z0.b 13; CHECK-NEXT: ptrue p0.s 14; CHECK-NEXT: sunpklo z1.h, z1.b 15; CHECK-NEXT: sunpklo z0.h, z0.b 16; CHECK-NEXT: sunpkhi z4.s, z2.h 17; CHECK-NEXT: sunpkhi z5.s, z3.h 18; CHECK-NEXT: sunpklo z2.s, z2.h 19; CHECK-NEXT: sunpklo z3.s, z3.h 20; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s 21; CHECK-NEXT: sunpkhi z5.s, z1.h 22; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s 23; CHECK-NEXT: sunpkhi z3.s, z0.h 24; CHECK-NEXT: sunpklo z1.s, z1.h 25; CHECK-NEXT: sunpklo z0.s, z0.h 26; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z5.s 27; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s 28; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h 29; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h 30; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b 31; CHECK-NEXT: ret 32 %div = sdiv <vscale x 16 x i8> %a, %b 33 ret <vscale x 16 x i8> %div 34} 35 36define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 37; CHECK-LABEL: sdiv_i16: 38; CHECK: // %bb.0: 39; CHECK-NEXT: sunpkhi z2.s, z1.h 40; CHECK-NEXT: sunpkhi z3.s, z0.h 41; CHECK-NEXT: ptrue p0.s 42; CHECK-NEXT: sunpklo z1.s, z1.h 43; CHECK-NEXT: sunpklo z0.s, z0.h 44; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s 45; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s 46; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h 47; CHECK-NEXT: ret 48 %div = sdiv <vscale x 8 x i16> %a, %b 49 ret <vscale x 8 x i16> %div 50} 51 52define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 53; CHECK-LABEL: sdiv_i32: 54; CHECK: // %bb.0: 55; CHECK-NEXT: ptrue p0.s 56; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s 57; CHECK-NEXT: ret 58 %div = sdiv <vscale x 4 x i32> %a, %b 59 ret <vscale x 4 x i32> %div 60} 61 62define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 63; CHECK-LABEL: sdiv_i64: 64; CHECK: // %bb.0: 65; CHECK-NEXT: ptrue p0.d 66; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d 67; CHECK-NEXT: ret 68 %div = sdiv <vscale x 2 x i64> %a, %b 69 ret <vscale x 2 x i64> %div 70} 71 72define <vscale x 8 x i32> @sdiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) { 73; CHECK-LABEL: sdiv_split_i32: 74; CHECK: // %bb.0: 75; CHECK-NEXT: ptrue p0.s 76; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z2.s 77; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s 78; CHECK-NEXT: ret 79 %div = sdiv <vscale x 8 x i32> %a, %b 80 ret <vscale x 8 x i32> %div 81} 82 83define <vscale x 2 x i32> @sdiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 84; CHECK-LABEL: sdiv_widen_i32: 85; CHECK: // %bb.0: 86; CHECK-NEXT: ptrue p0.d 87; CHECK-NEXT: sxtw z1.d, p0/m, z1.d 88; CHECK-NEXT: sxtw z0.d, p0/m, z0.d 89; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d 90; CHECK-NEXT: ret 91 %div = sdiv <vscale x 2 x i32> %a, %b 92 ret <vscale x 2 x i32> %div 93} 94 95define <vscale x 4 x i64> @sdiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) { 96; CHECK-LABEL: sdiv_split_i64: 97; CHECK: // %bb.0: 98; CHECK-NEXT: ptrue p0.d 99; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z2.d 100; CHECK-NEXT: sdiv z1.d, p0/m, z1.d, z3.d 101; CHECK-NEXT: ret 102 %div = sdiv <vscale x 4 x i64> %a, %b 103 ret <vscale x 4 x i64> %div 104} 105 106; 107; SREM 108; 109 110define <vscale x 16 x i8> @srem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 111; CHECK-LABEL: srem_i8: 112; CHECK: // %bb.0: 113; CHECK-NEXT: sunpkhi z2.h, z1.b 114; CHECK-NEXT: sunpkhi z3.h, z0.b 115; CHECK-NEXT: ptrue p0.s 116; CHECK-NEXT: sunpklo z4.h, z1.b 117; CHECK-NEXT: sunpklo z5.h, z0.b 118; CHECK-NEXT: sunpkhi z6.s, z2.h 119; CHECK-NEXT: sunpkhi z7.s, z3.h 120; CHECK-NEXT: sunpklo z2.s, z2.h 121; CHECK-NEXT: sunpklo z3.s, z3.h 122; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s 123; CHECK-NEXT: sunpkhi z7.s, z4.h 124; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s 125; CHECK-NEXT: sunpkhi z3.s, z5.h 126; CHECK-NEXT: sunpklo z4.s, z4.h 127; CHECK-NEXT: sunpklo z5.s, z5.h 128; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z7.s 129; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s 130; CHECK-NEXT: uzp1 z2.h, z2.h, z6.h 131; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h 132; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b 133; CHECK-NEXT: ptrue p0.b 134; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b 135; CHECK-NEXT: ret 136 %div = srem <vscale x 16 x i8> %a, %b 137 ret <vscale x 16 x i8> %div 138} 139 140define <vscale x 8 x i16> @srem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 141; CHECK-LABEL: srem_i16: 142; CHECK: // %bb.0: 143; CHECK-NEXT: sunpkhi z2.s, z1.h 144; CHECK-NEXT: sunpkhi z3.s, z0.h 145; CHECK-NEXT: ptrue p0.s 146; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s 147; CHECK-NEXT: sunpklo z4.s, z1.h 148; CHECK-NEXT: sunpklo z5.s, z0.h 149; CHECK-NEXT: movprfx z3, z5 150; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z4.s 151; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h 152; CHECK-NEXT: ptrue p0.h 153; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h 154; CHECK-NEXT: ret 155 %div = srem <vscale x 8 x i16> %a, %b 156 ret <vscale x 8 x i16> %div 157} 158 159define <vscale x 4 x i32> @srem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 160; CHECK-LABEL: srem_i32: 161; CHECK: // %bb.0: 162; CHECK-NEXT: ptrue p0.s 163; CHECK-NEXT: movprfx z2, z0 164; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z1.s 165; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s 166; CHECK-NEXT: ret 167 %div = srem <vscale x 4 x i32> %a, %b 168 ret <vscale x 4 x i32> %div 169} 170 171define <vscale x 2 x i64> @srem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 172; CHECK-LABEL: srem_i64: 173; CHECK: // %bb.0: 174; CHECK-NEXT: ptrue p0.d 175; CHECK-NEXT: movprfx z2, z0 176; CHECK-NEXT: sdiv z2.d, p0/m, z2.d, z1.d 177; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d 178; CHECK-NEXT: ret 179 %div = srem <vscale x 2 x i64> %a, %b 180 ret <vscale x 2 x i64> %div 181} 182 183; 184; UDIV 185; 186 187define <vscale x 16 x i8> @udiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 188; CHECK-LABEL: udiv_i8: 189; CHECK: // %bb.0: 190; CHECK-NEXT: uunpkhi z2.h, z1.b 191; CHECK-NEXT: uunpkhi z3.h, z0.b 192; CHECK-NEXT: ptrue p0.s 193; CHECK-NEXT: uunpklo z1.h, z1.b 194; CHECK-NEXT: uunpklo z0.h, z0.b 195; CHECK-NEXT: uunpkhi z4.s, z2.h 196; CHECK-NEXT: uunpkhi z5.s, z3.h 197; CHECK-NEXT: uunpklo z2.s, z2.h 198; CHECK-NEXT: uunpklo z3.s, z3.h 199; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s 200; CHECK-NEXT: uunpkhi z5.s, z1.h 201; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s 202; CHECK-NEXT: uunpkhi z3.s, z0.h 203; CHECK-NEXT: uunpklo z1.s, z1.h 204; CHECK-NEXT: uunpklo z0.s, z0.h 205; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z5.s 206; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s 207; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h 208; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h 209; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b 210; CHECK-NEXT: ret 211 %div = udiv <vscale x 16 x i8> %a, %b 212 ret <vscale x 16 x i8> %div 213} 214 215define <vscale x 8 x i16> @udiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 216; CHECK-LABEL: udiv_i16: 217; CHECK: // %bb.0: 218; CHECK-NEXT: uunpkhi z2.s, z1.h 219; CHECK-NEXT: uunpkhi z3.s, z0.h 220; CHECK-NEXT: ptrue p0.s 221; CHECK-NEXT: uunpklo z1.s, z1.h 222; CHECK-NEXT: uunpklo z0.s, z0.h 223; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s 224; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s 225; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h 226; CHECK-NEXT: ret 227 %div = udiv <vscale x 8 x i16> %a, %b 228 ret <vscale x 8 x i16> %div 229} 230 231define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 232; CHECK-LABEL: udiv_i32: 233; CHECK: // %bb.0: 234; CHECK-NEXT: ptrue p0.s 235; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s 236; CHECK-NEXT: ret 237 %div = udiv <vscale x 4 x i32> %a, %b 238 ret <vscale x 4 x i32> %div 239} 240 241define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 242; CHECK-LABEL: udiv_i64: 243; CHECK: // %bb.0: 244; CHECK-NEXT: ptrue p0.d 245; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d 246; CHECK-NEXT: ret 247 %div = udiv <vscale x 2 x i64> %a, %b 248 ret <vscale x 2 x i64> %div 249} 250 251define <vscale x 8 x i32> @udiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) { 252; CHECK-LABEL: udiv_split_i32: 253; CHECK: // %bb.0: 254; CHECK-NEXT: ptrue p0.s 255; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z2.s 256; CHECK-NEXT: udiv z1.s, p0/m, z1.s, z3.s 257; CHECK-NEXT: ret 258 %div = udiv <vscale x 8 x i32> %a, %b 259 ret <vscale x 8 x i32> %div 260} 261 262define <vscale x 2 x i32> @udiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 263; CHECK-LABEL: udiv_widen_i32: 264; CHECK: // %bb.0: 265; CHECK-NEXT: ptrue p0.d 266; CHECK-NEXT: and z1.d, z1.d, #0xffffffff 267; CHECK-NEXT: and z0.d, z0.d, #0xffffffff 268; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d 269; CHECK-NEXT: ret 270 %div = udiv <vscale x 2 x i32> %a, %b 271 ret <vscale x 2 x i32> %div 272} 273 274define <vscale x 4 x i64> @udiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) { 275; CHECK-LABEL: udiv_split_i64: 276; CHECK: // %bb.0: 277; CHECK-NEXT: ptrue p0.d 278; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z2.d 279; CHECK-NEXT: udiv z1.d, p0/m, z1.d, z3.d 280; CHECK-NEXT: ret 281 %div = udiv <vscale x 4 x i64> %a, %b 282 ret <vscale x 4 x i64> %div 283} 284 285 286; 287; UREM 288; 289 290define <vscale x 16 x i8> @urem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 291; CHECK-LABEL: urem_i8: 292; CHECK: // %bb.0: 293; CHECK-NEXT: uunpkhi z2.h, z1.b 294; CHECK-NEXT: uunpkhi z3.h, z0.b 295; CHECK-NEXT: ptrue p0.s 296; CHECK-NEXT: uunpklo z4.h, z1.b 297; CHECK-NEXT: uunpklo z5.h, z0.b 298; CHECK-NEXT: uunpkhi z6.s, z2.h 299; CHECK-NEXT: uunpkhi z7.s, z3.h 300; CHECK-NEXT: uunpklo z2.s, z2.h 301; CHECK-NEXT: uunpklo z3.s, z3.h 302; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s 303; CHECK-NEXT: uunpkhi z7.s, z4.h 304; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s 305; CHECK-NEXT: uunpkhi z3.s, z5.h 306; CHECK-NEXT: uunpklo z4.s, z4.h 307; CHECK-NEXT: uunpklo z5.s, z5.h 308; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z7.s 309; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s 310; CHECK-NEXT: uzp1 z2.h, z2.h, z6.h 311; CHECK-NEXT: uzp1 z3.h, z4.h, z3.h 312; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b 313; CHECK-NEXT: ptrue p0.b 314; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b 315; CHECK-NEXT: ret 316 %div = urem <vscale x 16 x i8> %a, %b 317 ret <vscale x 16 x i8> %div 318} 319 320define <vscale x 8 x i16> @urem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 321; CHECK-LABEL: urem_i16: 322; CHECK: // %bb.0: 323; CHECK-NEXT: uunpkhi z2.s, z1.h 324; CHECK-NEXT: uunpkhi z3.s, z0.h 325; CHECK-NEXT: ptrue p0.s 326; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s 327; CHECK-NEXT: uunpklo z4.s, z1.h 328; CHECK-NEXT: uunpklo z5.s, z0.h 329; CHECK-NEXT: movprfx z3, z5 330; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z4.s 331; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h 332; CHECK-NEXT: ptrue p0.h 333; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h 334; CHECK-NEXT: ret 335 %div = urem <vscale x 8 x i16> %a, %b 336 ret <vscale x 8 x i16> %div 337} 338 339define <vscale x 4 x i32> @urem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 340; CHECK-LABEL: urem_i32: 341; CHECK: // %bb.0: 342; CHECK-NEXT: ptrue p0.s 343; CHECK-NEXT: movprfx z2, z0 344; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s 345; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s 346; CHECK-NEXT: ret 347 %div = urem <vscale x 4 x i32> %a, %b 348 ret <vscale x 4 x i32> %div 349} 350 351define <vscale x 2 x i64> @urem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 352; CHECK-LABEL: urem_i64: 353; CHECK: // %bb.0: 354; CHECK-NEXT: ptrue p0.d 355; CHECK-NEXT: movprfx z2, z0 356; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d 357; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d 358; CHECK-NEXT: ret 359 %div = urem <vscale x 2 x i64> %a, %b 360 ret <vscale x 2 x i64> %div 361} 362 363; 364; SMIN 365; 366 367define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 368; CHECK-LABEL: smin_i8: 369; CHECK: // %bb.0: 370; CHECK-NEXT: ptrue p0.b 371; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b 372; CHECK-NEXT: ret 373 %cmp = icmp slt <vscale x 16 x i8> %a, %b 374 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b 375 ret <vscale x 16 x i8> %min 376} 377 378define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 379; CHECK-LABEL: smin_i16: 380; CHECK: // %bb.0: 381; CHECK-NEXT: ptrue p0.h 382; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h 383; CHECK-NEXT: ret 384 %cmp = icmp slt <vscale x 8 x i16> %a, %b 385 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b 386 ret <vscale x 8 x i16> %min 387} 388 389define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 390; CHECK-LABEL: smin_i32: 391; CHECK: // %bb.0: 392; CHECK-NEXT: ptrue p0.s 393; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s 394; CHECK-NEXT: ret 395 %cmp = icmp slt <vscale x 4 x i32> %a, %b 396 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b 397 ret <vscale x 4 x i32> %min 398} 399 400define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 401; CHECK-LABEL: smin_i64: 402; CHECK: // %bb.0: 403; CHECK-NEXT: ptrue p0.d 404; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d 405; CHECK-NEXT: ret 406 %cmp = icmp slt <vscale x 2 x i64> %a, %b 407 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b 408 ret <vscale x 2 x i64> %min 409} 410 411define <vscale x 32 x i8> @smin_split_i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { 412; CHECK-LABEL: smin_split_i8: 413; CHECK: // %bb.0: 414; CHECK-NEXT: ptrue p0.b 415; CHECK-NEXT: smin z0.b, p0/m, z0.b, z2.b 416; CHECK-NEXT: smin z1.b, p0/m, z1.b, z3.b 417; CHECK-NEXT: ret 418 %cmp = icmp slt <vscale x 32 x i8> %a, %b 419 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b 420 ret <vscale x 32 x i8> %min 421} 422 423define <vscale x 32 x i16> @smin_split_i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) { 424; CHECK-LABEL: smin_split_i16: 425; CHECK: // %bb.0: 426; CHECK-NEXT: ptrue p0.h 427; CHECK-NEXT: smin z0.h, p0/m, z0.h, z4.h 428; CHECK-NEXT: smin z1.h, p0/m, z1.h, z5.h 429; CHECK-NEXT: smin z2.h, p0/m, z2.h, z6.h 430; CHECK-NEXT: smin z3.h, p0/m, z3.h, z7.h 431; CHECK-NEXT: ret 432 %cmp = icmp slt <vscale x 32 x i16> %a, %b 433 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b 434 ret <vscale x 32 x i16> %min 435} 436 437define <vscale x 8 x i32> @smin_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) { 438; CHECK-LABEL: smin_split_i32: 439; CHECK: // %bb.0: 440; CHECK-NEXT: ptrue p0.s 441; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s 442; CHECK-NEXT: smin z1.s, p0/m, z1.s, z3.s 443; CHECK-NEXT: ret 444 %cmp = icmp slt <vscale x 8 x i32> %a, %b 445 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b 446 ret <vscale x 8 x i32> %min 447} 448 449define <vscale x 4 x i64> @smin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) { 450; CHECK-LABEL: smin_split_i64: 451; CHECK: // %bb.0: 452; CHECK-NEXT: ptrue p0.d 453; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d 454; CHECK-NEXT: smin z1.d, p0/m, z1.d, z3.d 455; CHECK-NEXT: ret 456 %cmp = icmp slt <vscale x 4 x i64> %a, %b 457 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b 458 ret <vscale x 4 x i64> %min 459} 460 461define <vscale x 8 x i8> @smin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { 462; CHECK-LABEL: smin_promote_i8: 463; CHECK: // %bb.0: 464; CHECK-NEXT: ptrue p0.h 465; CHECK-NEXT: sxtb z1.h, p0/m, z1.h 466; CHECK-NEXT: sxtb z0.h, p0/m, z0.h 467; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h 468; CHECK-NEXT: ret 469 %cmp = icmp slt <vscale x 8 x i8> %a, %b 470 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b 471 ret <vscale x 8 x i8> %min 472} 473 474define <vscale x 4 x i16> @smin_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) { 475; CHECK-LABEL: smin_promote_i16: 476; CHECK: // %bb.0: 477; CHECK-NEXT: ptrue p0.s 478; CHECK-NEXT: sxth z1.s, p0/m, z1.s 479; CHECK-NEXT: sxth z0.s, p0/m, z0.s 480; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s 481; CHECK-NEXT: ret 482 %cmp = icmp slt <vscale x 4 x i16> %a, %b 483 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b 484 ret <vscale x 4 x i16> %min 485} 486 487define <vscale x 2 x i32> @smin_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 488; CHECK-LABEL: smin_promote_i32: 489; CHECK: // %bb.0: 490; CHECK-NEXT: ptrue p0.d 491; CHECK-NEXT: sxtw z1.d, p0/m, z1.d 492; CHECK-NEXT: sxtw z0.d, p0/m, z0.d 493; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d 494; CHECK-NEXT: ret 495 %cmp = icmp slt <vscale x 2 x i32> %a, %b 496 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b 497 ret <vscale x 2 x i32> %min 498} 499 500; 501; UMIN 502; 503 504define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 505; CHECK-LABEL: umin_i8: 506; CHECK: // %bb.0: 507; CHECK-NEXT: ptrue p0.b 508; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b 509; CHECK-NEXT: ret 510 %cmp = icmp ult <vscale x 16 x i8> %a, %b 511 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b 512 ret <vscale x 16 x i8> %min 513} 514 515define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 516; CHECK-LABEL: umin_i16: 517; CHECK: // %bb.0: 518; CHECK-NEXT: ptrue p0.h 519; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h 520; CHECK-NEXT: ret 521 %cmp = icmp ult <vscale x 8 x i16> %a, %b 522 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b 523 ret <vscale x 8 x i16> %min 524} 525 526define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 527; CHECK-LABEL: umin_i32: 528; CHECK: // %bb.0: 529; CHECK-NEXT: ptrue p0.s 530; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s 531; CHECK-NEXT: ret 532 %cmp = icmp ult <vscale x 4 x i32> %a, %b 533 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b 534 ret <vscale x 4 x i32> %min 535} 536 537define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 538; CHECK-LABEL: umin_i64: 539; CHECK: // %bb.0: 540; CHECK-NEXT: ptrue p0.d 541; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d 542; CHECK-NEXT: ret 543 %cmp = icmp ult <vscale x 2 x i64> %a, %b 544 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b 545 ret <vscale x 2 x i64> %min 546} 547 548define <vscale x 4 x i64> @umin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) { 549; CHECK-LABEL: umin_split_i64: 550; CHECK: // %bb.0: 551; CHECK-NEXT: ptrue p0.d 552; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d 553; CHECK-NEXT: umin z1.d, p0/m, z1.d, z3.d 554; CHECK-NEXT: ret 555 %cmp = icmp ult <vscale x 4 x i64> %a, %b 556 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b 557 ret <vscale x 4 x i64> %min 558} 559 560define <vscale x 8 x i8> @umin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) { 561; CHECK-LABEL: umin_promote_i8: 562; CHECK: // %bb.0: 563; CHECK-NEXT: ptrue p0.h 564; CHECK-NEXT: and z1.h, z1.h, #0xff 565; CHECK-NEXT: and z0.h, z0.h, #0xff 566; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h 567; CHECK-NEXT: ret 568 %cmp = icmp ult <vscale x 8 x i8> %a, %b 569 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b 570 ret <vscale x 8 x i8> %min 571} 572 573; 574; SMAX 575; 576 577define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 578; CHECK-LABEL: smax_i8: 579; CHECK: // %bb.0: 580; CHECK-NEXT: ptrue p0.b 581; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b 582; CHECK-NEXT: ret 583 %cmp = icmp sgt <vscale x 16 x i8> %a, %b 584 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b 585 ret <vscale x 16 x i8> %max 586} 587 588define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 589; CHECK-LABEL: smax_i16: 590; CHECK: // %bb.0: 591; CHECK-NEXT: ptrue p0.h 592; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h 593; CHECK-NEXT: ret 594 %cmp = icmp sgt <vscale x 8 x i16> %a, %b 595 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b 596 ret <vscale x 8 x i16> %max 597} 598 599define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 600; CHECK-LABEL: smax_i32: 601; CHECK: // %bb.0: 602; CHECK-NEXT: ptrue p0.s 603; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s 604; CHECK-NEXT: ret 605 %cmp = icmp sgt <vscale x 4 x i32> %a, %b 606 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b 607 ret <vscale x 4 x i32> %max 608} 609 610define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 611; CHECK-LABEL: smax_i64: 612; CHECK: // %bb.0: 613; CHECK-NEXT: ptrue p0.d 614; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d 615; CHECK-NEXT: ret 616 %cmp = icmp sgt <vscale x 2 x i64> %a, %b 617 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b 618 ret <vscale x 2 x i64> %max 619} 620 621define <vscale x 8 x i32> @smax_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) { 622; CHECK-LABEL: smax_split_i32: 623; CHECK: // %bb.0: 624; CHECK-NEXT: ptrue p0.s 625; CHECK-NEXT: smax z0.s, p0/m, z0.s, z2.s 626; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s 627; CHECK-NEXT: ret 628 %cmp = icmp sgt <vscale x 8 x i32> %a, %b 629 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b 630 ret <vscale x 8 x i32> %max 631} 632 633define <vscale x 4 x i16> @smax_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) { 634; CHECK-LABEL: smax_promote_i16: 635; CHECK: // %bb.0: 636; CHECK-NEXT: ptrue p0.s 637; CHECK-NEXT: sxth z1.s, p0/m, z1.s 638; CHECK-NEXT: sxth z0.s, p0/m, z0.s 639; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s 640; CHECK-NEXT: ret 641 %cmp = icmp sgt <vscale x 4 x i16> %a, %b 642 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b 643 ret <vscale x 4 x i16> %max 644} 645 646; 647; UMAX 648; 649 650define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { 651; CHECK-LABEL: umax_i8: 652; CHECK: // %bb.0: 653; CHECK-NEXT: ptrue p0.b 654; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b 655; CHECK-NEXT: ret 656 %cmp = icmp ugt <vscale x 16 x i8> %a, %b 657 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b 658 ret <vscale x 16 x i8> %max 659} 660 661define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { 662; CHECK-LABEL: umax_i16: 663; CHECK: // %bb.0: 664; CHECK-NEXT: ptrue p0.h 665; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h 666; CHECK-NEXT: ret 667 %cmp = icmp ugt <vscale x 8 x i16> %a, %b 668 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b 669 ret <vscale x 8 x i16> %max 670} 671 672define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { 673; CHECK-LABEL: umax_i32: 674; CHECK: // %bb.0: 675; CHECK-NEXT: ptrue p0.s 676; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s 677; CHECK-NEXT: ret 678 %cmp = icmp ugt <vscale x 4 x i32> %a, %b 679 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b 680 ret <vscale x 4 x i32> %max 681} 682 683define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { 684; CHECK-LABEL: umax_i64: 685; CHECK: // %bb.0: 686; CHECK-NEXT: ptrue p0.d 687; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d 688; CHECK-NEXT: ret 689 %cmp = icmp ugt <vscale x 2 x i64> %a, %b 690 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b 691 ret <vscale x 2 x i64> %max 692} 693 694define <vscale x 16 x i16> @umax_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) { 695; CHECK-LABEL: umax_split_i16: 696; CHECK: // %bb.0: 697; CHECK-NEXT: ptrue p0.h 698; CHECK-NEXT: umax z0.h, p0/m, z0.h, z2.h 699; CHECK-NEXT: umax z1.h, p0/m, z1.h, z3.h 700; CHECK-NEXT: ret 701 %cmp = icmp ugt <vscale x 16 x i16> %a, %b 702 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b 703 ret <vscale x 16 x i16> %max 704} 705 706define <vscale x 2 x i32> @umax_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { 707; CHECK-LABEL: umax_promote_i32: 708; CHECK: // %bb.0: 709; CHECK-NEXT: ptrue p0.d 710; CHECK-NEXT: and z1.d, z1.d, #0xffffffff 711; CHECK-NEXT: and z0.d, z0.d, #0xffffffff 712; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d 713; CHECK-NEXT: ret 714 %cmp = icmp ugt <vscale x 2 x i32> %a, %b 715 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b 716 ret <vscale x 2 x i32> %max 717} 718 719; 720; ASR 721; 722 723define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 724; CHECK-LABEL: asr_i8: 725; CHECK: // %bb.0: 726; CHECK-NEXT: ptrue p0.b 727; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b 728; CHECK-NEXT: ret 729 %shr = ashr <vscale x 16 x i8> %a, %b 730 ret <vscale x 16 x i8> %shr 731} 732 733define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 734; CHECK-LABEL: asr_i16: 735; CHECK: // %bb.0: 736; CHECK-NEXT: ptrue p0.h 737; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h 738; CHECK-NEXT: ret 739 %shr = ashr <vscale x 8 x i16> %a, %b 740 ret <vscale x 8 x i16> %shr 741} 742 743define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 744; CHECK-LABEL: asr_i32: 745; CHECK: // %bb.0: 746; CHECK-NEXT: ptrue p0.s 747; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s 748; CHECK-NEXT: ret 749 %shr = ashr <vscale x 4 x i32> %a, %b 750 ret <vscale x 4 x i32> %shr 751} 752 753define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 754; CHECK-LABEL: asr_i64: 755; CHECK: // %bb.0: 756; CHECK-NEXT: ptrue p0.d 757; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d 758; CHECK-NEXT: ret 759 %shr = ashr <vscale x 2 x i64> %a, %b 760 ret <vscale x 2 x i64> %shr 761} 762 763define <vscale x 16 x i16> @asr_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b){ 764; CHECK-LABEL: asr_split_i16: 765; CHECK: // %bb.0: 766; CHECK-NEXT: ptrue p0.h 767; CHECK-NEXT: asr z0.h, p0/m, z0.h, z2.h 768; CHECK-NEXT: asr z1.h, p0/m, z1.h, z3.h 769; CHECK-NEXT: ret 770 %shr = ashr <vscale x 16 x i16> %a, %b 771 ret <vscale x 16 x i16> %shr 772} 773 774define <vscale x 2 x i32> @asr_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b){ 775; CHECK-LABEL: asr_promote_i32: 776; CHECK: // %bb.0: 777; CHECK-NEXT: ptrue p0.d 778; CHECK-NEXT: sxtw z0.d, p0/m, z0.d 779; CHECK-NEXT: and z1.d, z1.d, #0xffffffff 780; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d 781; CHECK-NEXT: ret 782 %shr = ashr <vscale x 2 x i32> %a, %b 783 ret <vscale x 2 x i32> %shr 784} 785 786; 787; ASRR 788; 789 790define <vscale x 16 x i8> @asrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 791; CHECK-LABEL: asrr_i8: 792; CHECK: // %bb.0: 793; CHECK-NEXT: ptrue p0.b 794; CHECK-NEXT: asrr z0.b, p0/m, z0.b, z1.b 795; CHECK-NEXT: ret 796 %shr = ashr <vscale x 16 x i8> %b, %a 797 ret <vscale x 16 x i8> %shr 798} 799 800define <vscale x 8 x i16> @asrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 801; CHECK-LABEL: asrr_i16: 802; CHECK: // %bb.0: 803; CHECK-NEXT: ptrue p0.h 804; CHECK-NEXT: asrr z0.h, p0/m, z0.h, z1.h 805; CHECK-NEXT: ret 806 %shr = ashr <vscale x 8 x i16> %b, %a 807 ret <vscale x 8 x i16> %shr 808} 809 810define <vscale x 4 x i32> @asrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 811; CHECK-LABEL: asrr_i32: 812; CHECK: // %bb.0: 813; CHECK-NEXT: ptrue p0.s 814; CHECK-NEXT: asrr z0.s, p0/m, z0.s, z1.s 815; CHECK-NEXT: ret 816 %shr = ashr <vscale x 4 x i32> %b, %a 817 ret <vscale x 4 x i32> %shr 818} 819 820define <vscale x 2 x i64> @asrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 821; CHECK-LABEL: asrr_i64: 822; CHECK: // %bb.0: 823; CHECK-NEXT: ptrue p0.d 824; CHECK-NEXT: asrr z0.d, p0/m, z0.d, z1.d 825; CHECK-NEXT: ret 826 %shr = ashr <vscale x 2 x i64> %b, %a 827 ret <vscale x 2 x i64> %shr 828} 829 830; 831; LSL 832; 833 834define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 835; CHECK-LABEL: lsl_i8: 836; CHECK: // %bb.0: 837; CHECK-NEXT: ptrue p0.b 838; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b 839; CHECK-NEXT: ret 840 %shl = shl <vscale x 16 x i8> %a, %b 841 ret <vscale x 16 x i8> %shl 842} 843 844define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 845; CHECK-LABEL: lsl_i16: 846; CHECK: // %bb.0: 847; CHECK-NEXT: ptrue p0.h 848; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h 849; CHECK-NEXT: ret 850 %shl = shl <vscale x 8 x i16> %a, %b 851 ret <vscale x 8 x i16> %shl 852} 853 854define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 855; CHECK-LABEL: lsl_i32: 856; CHECK: // %bb.0: 857; CHECK-NEXT: ptrue p0.s 858; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s 859; CHECK-NEXT: ret 860 %shl = shl <vscale x 4 x i32> %a, %b 861 ret <vscale x 4 x i32> %shl 862} 863 864define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 865; CHECK-LABEL: lsl_i64: 866; CHECK: // %bb.0: 867; CHECK-NEXT: ptrue p0.d 868; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d 869; CHECK-NEXT: ret 870 %shl = shl <vscale x 2 x i64> %a, %b 871 ret <vscale x 2 x i64> %shl 872} 873 874define <vscale x 4 x i64> @lsl_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b){ 875; CHECK-LABEL: lsl_split_i64: 876; CHECK: // %bb.0: 877; CHECK-NEXT: ptrue p0.d 878; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z2.d 879; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d 880; CHECK-NEXT: ret 881 %shl = shl <vscale x 4 x i64> %a, %b 882 ret <vscale x 4 x i64> %shl 883} 884 885define <vscale x 4 x i16> @lsl_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b){ 886; CHECK-LABEL: lsl_promote_i16: 887; CHECK: // %bb.0: 888; CHECK-NEXT: ptrue p0.s 889; CHECK-NEXT: and z1.s, z1.s, #0xffff 890; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s 891; CHECK-NEXT: ret 892 %shl = shl <vscale x 4 x i16> %a, %b 893 ret <vscale x 4 x i16> %shl 894} 895 896; 897; LSLR 898; 899 900define <vscale x 16 x i8> @lslr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 901; CHECK-LABEL: lslr_i8: 902; CHECK: // %bb.0: 903; CHECK-NEXT: ptrue p0.b 904; CHECK-NEXT: lslr z0.b, p0/m, z0.b, z1.b 905; CHECK-NEXT: ret 906 %shl = shl <vscale x 16 x i8> %b, %a 907 ret <vscale x 16 x i8> %shl 908} 909 910define <vscale x 8 x i16> @lslr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 911; CHECK-LABEL: lslr_i16: 912; CHECK: // %bb.0: 913; CHECK-NEXT: ptrue p0.h 914; CHECK-NEXT: lslr z0.h, p0/m, z0.h, z1.h 915; CHECK-NEXT: ret 916 %shl = shl <vscale x 8 x i16> %b, %a 917 ret <vscale x 8 x i16> %shl 918} 919 920define <vscale x 4 x i32> @lslr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 921; CHECK-LABEL: lslr_i32: 922; CHECK: // %bb.0: 923; CHECK-NEXT: ptrue p0.s 924; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z1.s 925; CHECK-NEXT: ret 926 %shl = shl <vscale x 4 x i32> %b, %a 927 ret <vscale x 4 x i32> %shl 928} 929 930define <vscale x 2 x i64> @lslr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 931; CHECK-LABEL: lslr_i64: 932; CHECK: // %bb.0: 933; CHECK-NEXT: ptrue p0.d 934; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z1.d 935; CHECK-NEXT: ret 936 %shl = shl <vscale x 2 x i64> %b, %a 937 ret <vscale x 2 x i64> %shl 938} 939 940; 941; LSR 942; 943 944define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 945; CHECK-LABEL: lsr_i8: 946; CHECK: // %bb.0: 947; CHECK-NEXT: ptrue p0.b 948; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b 949; CHECK-NEXT: ret 950 %shr = lshr <vscale x 16 x i8> %a, %b 951 ret <vscale x 16 x i8> %shr 952} 953 954define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 955; CHECK-LABEL: lsr_i16: 956; CHECK: // %bb.0: 957; CHECK-NEXT: ptrue p0.h 958; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h 959; CHECK-NEXT: ret 960 %shr = lshr <vscale x 8 x i16> %a, %b 961 ret <vscale x 8 x i16> %shr 962} 963 964define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 965; CHECK-LABEL: lsr_i32: 966; CHECK: // %bb.0: 967; CHECK-NEXT: ptrue p0.s 968; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s 969; CHECK-NEXT: ret 970 %shr = lshr <vscale x 4 x i32> %a, %b 971 ret <vscale x 4 x i32> %shr 972} 973 974define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 975; CHECK-LABEL: lsr_i64: 976; CHECK: // %bb.0: 977; CHECK-NEXT: ptrue p0.d 978; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d 979; CHECK-NEXT: ret 980 %shr = lshr <vscale x 2 x i64> %a, %b 981 ret <vscale x 2 x i64> %shr 982} 983 984define <vscale x 8 x i8> @lsr_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b){ 985; CHECK-LABEL: lsr_promote_i8: 986; CHECK: // %bb.0: 987; CHECK-NEXT: ptrue p0.h 988; CHECK-NEXT: and z1.h, z1.h, #0xff 989; CHECK-NEXT: and z0.h, z0.h, #0xff 990; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h 991; CHECK-NEXT: ret 992 %shr = lshr <vscale x 8 x i8> %a, %b 993 ret <vscale x 8 x i8> %shr 994} 995 996define <vscale x 8 x i32> @lsr_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b){ 997; CHECK-LABEL: lsr_split_i32: 998; CHECK: // %bb.0: 999; CHECK-NEXT: ptrue p0.s 1000; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z2.s 1001; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z3.s 1002; CHECK-NEXT: ret 1003 %shr = lshr <vscale x 8 x i32> %a, %b 1004 ret <vscale x 8 x i32> %shr 1005} 1006 1007; 1008; LSRR 1009; 1010 1011define <vscale x 16 x i8> @lsrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){ 1012; CHECK-LABEL: lsrr_i8: 1013; CHECK: // %bb.0: 1014; CHECK-NEXT: ptrue p0.b 1015; CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z1.b 1016; CHECK-NEXT: ret 1017 %shr = lshr <vscale x 16 x i8> %b, %a 1018 ret <vscale x 16 x i8> %shr 1019} 1020 1021define <vscale x 8 x i16> @lsrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){ 1022; CHECK-LABEL: lsrr_i16: 1023; CHECK: // %bb.0: 1024; CHECK-NEXT: ptrue p0.h 1025; CHECK-NEXT: lsrr z0.h, p0/m, z0.h, z1.h 1026; CHECK-NEXT: ret 1027 %shr = lshr <vscale x 8 x i16> %b, %a 1028 ret <vscale x 8 x i16> %shr 1029} 1030 1031define <vscale x 4 x i32> @lsrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){ 1032; CHECK-LABEL: lsrr_i32: 1033; CHECK: // %bb.0: 1034; CHECK-NEXT: ptrue p0.s 1035; CHECK-NEXT: lsrr z0.s, p0/m, z0.s, z1.s 1036; CHECK-NEXT: ret 1037 %shr = lshr <vscale x 4 x i32> %b, %a 1038 ret <vscale x 4 x i32> %shr 1039} 1040 1041define <vscale x 2 x i64> @lsrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){ 1042; CHECK-LABEL: lsrr_i64: 1043; CHECK: // %bb.0: 1044; CHECK-NEXT: ptrue p0.d 1045; CHECK-NEXT: lsrr z0.d, p0/m, z0.d, z1.d 1046; CHECK-NEXT: ret 1047 %shr = lshr <vscale x 2 x i64> %b, %a 1048 ret <vscale x 2 x i64> %shr 1049} 1050 1051; 1052; CMP 1053; 1054 1055define <vscale x 32 x i1> @cmp_split_32(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) { 1056; CHECK-LABEL: cmp_split_32: 1057; CHECK: // %bb.0: 1058; CHECK-NEXT: ptrue p1.b 1059; CHECK-NEXT: cmpgt p0.b, p1/z, z2.b, z0.b 1060; CHECK-NEXT: cmpgt p1.b, p1/z, z3.b, z1.b 1061; CHECK-NEXT: ret 1062 %cmp = icmp slt <vscale x 32 x i8> %a, %b 1063 ret <vscale x 32 x i1> %cmp 1064} 1065 1066define <vscale x 64 x i1> @cmp_split_64(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) { 1067; CHECK-LABEL: cmp_split_64: 1068; CHECK: // %bb.0: 1069; CHECK-NEXT: ptrue p3.b 1070; CHECK-NEXT: cmpgt p0.b, p3/z, z0.b, z4.b 1071; CHECK-NEXT: cmpgt p1.b, p3/z, z1.b, z5.b 1072; CHECK-NEXT: cmpgt p2.b, p3/z, z2.b, z6.b 1073; CHECK-NEXT: cmpgt p3.b, p3/z, z3.b, z7.b 1074; CHECK-NEXT: ret 1075 %cmp = icmp sgt <vscale x 64 x i8> %a, %b 1076 ret <vscale x 64 x i1> %cmp 1077} 1078