1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: add_nullptr_shl_add
6tracksRegLiveness: true
7body:             |
8  bb.0:
9    liveins: $sgpr0
10
11    ; CHECK-LABEL: name: add_nullptr_shl_add
12    ; CHECK: liveins: $sgpr0
13    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
14    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
15    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
16    ; CHECK: $vgpr0 = COPY [[SHL]](s32)
17    %0:_(s32) = COPY $sgpr0
18    %1:_(s32) = G_CONSTANT i32 3
19    %2:_(s32) = G_SHL %0, %1(s32)
20    %3:_(p3) = G_CONSTANT i32 0
21    %4:_(p3) = G_PTR_ADD %3, %2(s32)
22    %5:_(s32) = G_PTRTOINT %4(p3)
23    $vgpr0 = COPY %5(s32)
24
25...
26
27---
28name: add_nullptr_mul_add
29tracksRegLiveness: true
30body:             |
31  bb.0:
32    liveins: $vgpr0, $vgpr1
33
34    ; CHECK-LABEL: name: add_nullptr_mul_add
35    ; CHECK: liveins: $vgpr0, $vgpr1
36    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
37    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
38    ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
39    ; CHECK: $vgpr0 = COPY [[MUL]](s32)
40    %0:_(s32) = COPY $vgpr0
41    %1:_(s32) = COPY $vgpr1
42    %2:_(p3) = G_CONSTANT i32 0
43    %3:_(s32) = G_MUL %0:_, %1:_
44    %4:_(p3) = G_PTR_ADD %2:_, %3:_(s32)
45    %5:_(s32) = G_PTRTOINT %4:_(p3)
46    $vgpr0 = COPY %5:_(s32)
47
48...
49
50---
51name: add_nullptr_vec_all_zero
52tracksRegLiveness: true
53body:             |
54  bb.0:
55    liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
56
57    ; CHECK-LABEL: name: add_nullptr_vec_all_zero
58    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
59    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
60    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
61    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr3
62    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
63    ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
64    ; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](<2 x s32>)
65    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
66    %1:_(s32) = COPY $vgpr2
67    %2:_(s32) = COPY $vgpr3
68    %3:_(<2 x s32>) = G_BUILD_VECTOR %1:_(s32), %2:_(s32)
69    %4:_(<2 x s32>) = G_SHL %0, %3(<2 x s32>)
70    %5:_(p3) = G_CONSTANT i32 0
71    %6:_(<2 x p3>) = G_BUILD_VECTOR %5:_(p3), %5:_(p3)
72    %7:_(<2 x p3>) = G_PTR_ADD %6, %4(<2 x s32>)
73    %8:_(<2 x s32>) = G_PTRTOINT %7(<2 x p3>)
74    $vgpr0_vgpr1 = COPY %8(<2 x s32>)
75
76...
77