1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            narrow_ashr_s64_32_s64amt
6tracksRegLiveness: true
7body:             |
8  bb.0:
9    liveins: $vgpr0_vgpr1
10
11    ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt
12    ; CHECK: liveins: $vgpr0_vgpr1
13    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
14    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
15    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
16    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
17    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
18    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
19    %0:_(s64) = COPY $vgpr0_vgpr1
20    %1:_(s64) = G_CONSTANT i64 32
21    %2:_(s64) = G_ASHR %0, %1
22    $vgpr0_vgpr1 = COPY %2
23...
24
25---
26name:            narrow_ashr_s64_32
27tracksRegLiveness: true
28body:             |
29  bb.0:
30    liveins: $vgpr0_vgpr1
31
32    ; CHECK-LABEL: name: narrow_ashr_s64_32
33    ; CHECK: liveins: $vgpr0_vgpr1
34    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
35    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
36    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
37    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
38    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV1]](s32), [[ASHR]](s32)
39    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
40    %0:_(s64) = COPY $vgpr0_vgpr1
41    %1:_(s32) = G_CONSTANT i32 32
42    %2:_(s64) = G_ASHR %0, %1
43    $vgpr0_vgpr1 = COPY %2
44...
45
46---
47name:            narrow_ashr_s64_33
48tracksRegLiveness: true
49body:             |
50  bb.0:
51    liveins: $vgpr0_vgpr1
52
53    ; CHECK-LABEL: name: narrow_ashr_s64_33
54    ; CHECK: liveins: $vgpr0_vgpr1
55    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
56    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
57    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
58    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
59    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
60    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
61    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)
62    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
63    %0:_(s64) = COPY $vgpr0_vgpr1
64    %1:_(s32) = G_CONSTANT i32 33
65    %2:_(s64) = G_ASHR %0, %1
66    $vgpr0_vgpr1 = COPY %2
67...
68
69---
70name:            narrow_ashr_s64_31
71tracksRegLiveness: true
72body:             |
73  bb.0:
74    liveins: $vgpr0_vgpr1
75
76    ; CHECK-LABEL: name: narrow_ashr_s64_31
77    ; CHECK: liveins: $vgpr0_vgpr1
78    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
79    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
80    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
81    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
82    %0:_(s64) = COPY $vgpr0_vgpr1
83    %1:_(s32) = G_CONSTANT i32 31
84    %2:_(s64) = G_ASHR %0, %1
85    $vgpr0_vgpr1 = COPY %2
86...
87
88---
89name:            narrow_ashr_s64_63
90tracksRegLiveness: true
91body:             |
92  bb.0:
93    liveins: $vgpr0_vgpr1
94
95    ; CHECK-LABEL: name: narrow_ashr_s64_63
96    ; CHECK: liveins: $vgpr0_vgpr1
97    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
98    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
99    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
100    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
101    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
102    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
103    %0:_(s64) = COPY $vgpr0_vgpr1
104    %1:_(s32) = G_CONSTANT i32 63
105    %2:_(s64) = G_ASHR %0, %1
106    $vgpr0_vgpr1 = COPY %2
107...
108
109---
110name:            narrow_ashr_s64_64
111tracksRegLiveness: true
112body:             |
113  bb.0:
114    liveins: $vgpr0_vgpr1
115
116    ; CHECK-LABEL: name: narrow_ashr_s64_64
117    ; CHECK: liveins: $vgpr0_vgpr1
118    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
119    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
120    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
121    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
122    %0:_(s64) = COPY $vgpr0_vgpr1
123    %1:_(s32) = G_CONSTANT i32 64
124    %2:_(s64) = G_ASHR %0, %1
125    $vgpr0_vgpr1 = COPY %2
126...
127
128---
129name:            narrow_ashr_s64_65
130tracksRegLiveness: true
131body:             |
132  bb.0:
133    liveins: $vgpr0_vgpr1
134
135    ; CHECK-LABEL: name: narrow_ashr_s64_65
136    ; CHECK: liveins: $vgpr0_vgpr1
137    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
138    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65
139    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
140    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
141    %0:_(s64) = COPY $vgpr0_vgpr1
142    %1:_(s32) = G_CONSTANT i32 65
143    %2:_(s64) = G_ASHR %0, %1
144    $vgpr0_vgpr1 = COPY %2
145...
146
147---
148name:            narrow_ashr_s32_16
149tracksRegLiveness: true
150body:             |
151  bb.0:
152    liveins: $vgpr0
153
154    ; CHECK-LABEL: name: narrow_ashr_s32_16
155    ; CHECK: liveins: $vgpr0
156    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
157    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
158    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
159    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
160    %0:_(s32) = COPY $vgpr0
161    %1:_(s32) = G_CONSTANT i32 16
162    %2:_(s32) = G_ASHR %0, %1
163    $vgpr0 = COPY %2
164...
165
166---
167name:            narrow_ashr_s32_17
168tracksRegLiveness: true
169body:             |
170  bb.0:
171    liveins: $vgpr0
172
173    ; CHECK-LABEL: name: narrow_ashr_s32_17
174    ; CHECK: liveins: $vgpr0
175    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
176    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
177    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
178    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
179    %0:_(s32) = COPY $vgpr0
180    %1:_(s32) = G_CONSTANT i32 17
181    %2:_(s32) = G_ASHR %0, %1
182    $vgpr0 = COPY %2
183...
184
185---
186name:            narrow_ashr_v2s32_17
187tracksRegLiveness: true
188body:             |
189  bb.0:
190    liveins: $vgpr0_vgpr1
191
192    ; CHECK-LABEL: name: narrow_ashr_v2s32_17
193    ; CHECK: liveins: $vgpr0_vgpr1
194    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
195    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
196    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
197    ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
198    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](<2 x s32>)
199    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
200    %1:_(s32) = G_CONSTANT i32 17
201    %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1
202    %3:_(<2 x s32>) = G_ASHR %0, %2
203    $vgpr0_vgpr1 = COPY %3
204...
205