1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            test_const_const_1
6tracksRegLiveness: true
7body:             |
8  bb.0:
9    ; CHECK-LABEL: name: test_const_const_1
10    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
11    ; CHECK: $sgpr0 = COPY [[C]](s32)
12    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
13    %0:_(s32) = G_CONSTANT i32 255
14    %1:_(s32) = G_CONSTANT i32 15
15    %2:_(s32) = G_OR %0(s32), %1(s32)
16    $sgpr0 = COPY %2(s32)
17    SI_RETURN_TO_EPILOG implicit $sgpr0
18...
19
20---
21name:            test_const_const_2
22tracksRegLiveness: true
23body:             |
24  bb.0:
25    ; CHECK-LABEL: name: test_const_const_2
26    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
27    ; CHECK: $vgpr0 = COPY [[C]](s32)
28    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
29    %0:_(s32) = G_CONSTANT i32 15
30    %1:_(s32) = G_CONSTANT i32 255
31    %2:_(s32) = G_OR %0(s32), %1(s32)
32    $vgpr0 = COPY %2(s32)
33    SI_RETURN_TO_EPILOG implicit $vgpr0
34...
35
36---
37name:            test_const_const_3
38tracksRegLiveness: true
39body:             |
40  bb.0:
41    ; CHECK-LABEL: name: test_const_const_3
42    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765
43    ; CHECK: $vgpr0 = COPY [[C]](s32)
44    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
45    %0:_(s32) = G_CONSTANT i32 1431655765
46    %1:_(s32) = G_CONSTANT i32 1145324612
47    %2:_(s32) = G_OR %1(s32), %0(s32)
48    $vgpr0 = COPY %2(s32)
49    SI_RETURN_TO_EPILOG implicit $vgpr0
50...
51
52---
53name:            test_or_or
54tracksRegLiveness: true
55body:             |
56  bb.0:
57    liveins: $vgpr0
58
59    ; CHECK-LABEL: name: test_or_or
60    ; CHECK: liveins: $vgpr0
61    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
62    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
63    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
64    ; CHECK: $vgpr0 = COPY [[OR]](s32)
65    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
66    %0:_(s32) = COPY $vgpr0
67    %1:_(s32) = G_CONSTANT i32 255
68    %2:_(s32) = G_CONSTANT i32 15
69    %3:_(s32) = G_OR %0, %1(s32)
70    %4:_(s32) = G_OR %3, %2
71    $vgpr0 = COPY %4(s32)
72    SI_RETURN_TO_EPILOG implicit $vgpr0
73...
74
75---
76name:            test_shl_xor_or
77tracksRegLiveness: true
78body:             |
79  bb.0:
80    liveins: $sgpr0
81
82    ; CHECK-LABEL: name: test_shl_xor_or
83    ; CHECK: liveins: $sgpr0
84    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
85    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
86    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
87    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
88    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
89    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
90    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
91    %0:_(s32) = COPY $sgpr0
92    %1:_(s32) = G_CONSTANT i32 5
93    %2:_(s32) = G_CONSTANT i32 -1
94    %3:_(s32) = G_CONSTANT i32 31
95    %4:_(s32) = G_SHL %0, %1(s32)
96    %5:_(s32) = G_XOR %4(s32), %2(s32)
97    %6:_(s32) = G_OR %5(s32), %3(s32)
98    $sgpr0 = COPY %6(s32)
99    SI_RETURN_TO_EPILOG implicit $sgpr0
100...
101
102---
103name:            test_lshr_xor_or
104tracksRegLiveness: true
105body:             |
106  bb.0:
107    liveins: $vgpr0
108
109    ; CHECK-LABEL: name: test_lshr_xor_or
110    ; CHECK: liveins: $vgpr0
111    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
112    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
113    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
114    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
115    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
116    ; CHECK: $vgpr0 = COPY [[XOR]](s32)
117    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
118    %0:_(s32) = COPY $vgpr0
119    %1:_(s32) = G_CONSTANT i32 5
120    %2:_(s32) = G_CONSTANT i32 -1
121    %3:_(s32) = G_CONSTANT i32 4160749568
122    %4:_(s32) = G_LSHR %0, %1(s32)
123    %5:_(s32) = G_XOR %4(s32), %2(s32)
124    %6:_(s32) = G_OR %5(s32), %3(s32)
125    $vgpr0 = COPY %6(s32)
126    SI_RETURN_TO_EPILOG implicit $vgpr0
127...
128
129---
130name:            test_or_non_const
131tracksRegLiveness: true
132body:             |
133  bb.0:
134    liveins: $sgpr0, $sgpr1
135
136    ; CHECK-LABEL: name: test_or_non_const
137    ; CHECK: liveins: $sgpr0, $sgpr1
138    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
139    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
140    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
141    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
142    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[LSHR]], [[C1]]
143    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
144    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
145    %0:_(s32) = COPY $sgpr0
146    %1:_(s32) = COPY $sgpr1
147    %2:_(s32) = G_CONSTANT i32 16
148    %3:_(s32) = G_CONSTANT i32 -1
149    %4:_(s32) = G_CONSTANT i32 4294901760
150    %5:_(s32) = G_LSHR %0, %2(s32)
151    %6:_(s32) = G_XOR %5, %3(s32)
152    %7:_(s32) = G_AND %1, %4(s32)
153    %8:_(s32) = G_OR %6, %7
154    $sgpr0 = COPY %8(s32)
155    SI_RETURN_TO_EPILOG implicit $sgpr0
156...
157