1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            test_const_const
6tracksRegLiveness: true
7body:             |
8  bb.0:
9    ; CHECK-LABEL: name: test_const_const
10    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
11    ; CHECK: $sgpr0 = COPY [[C]](s32)
12    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
13    %0:_(s32) = G_CONSTANT i32 15
14    %1:_(s32) = G_CONSTANT i32 255
15    %2:_(s32) = G_AND %0(s32), %1(s32)
16    $sgpr0 = COPY %2(s32)
17    SI_RETURN_TO_EPILOG implicit $sgpr0
18...
19
20---
21name:            test_const_const_2
22tracksRegLiveness: true
23body:             |
24  bb.0:
25    ; CHECK-LABEL: name: test_const_const_2
26    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
27    ; CHECK: $sgpr0 = COPY [[C]](s32)
28    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
29    %0:_(s32) = G_CONSTANT i32 255
30    %1:_(s32) = G_CONSTANT i32 15
31    %2:_(s32) = G_AND %0(s32), %1(s32)
32    $sgpr0 = COPY %2(s32)
33    SI_RETURN_TO_EPILOG implicit $sgpr0
34...
35
36---
37name:            test_const_const_3
38tracksRegLiveness: true
39body:             |
40  bb.0:
41    ; CHECK-LABEL: name: test_const_const_3
42    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
43    ; CHECK: $vgpr0 = COPY [[C]](s32)
44    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
45    %0:_(s32) = G_CONSTANT i32 2863311530
46    %1:_(s32) = G_CONSTANT i32 4008636142
47    %2:_(s32) = G_AND %0(s32), %1(s32)
48    $vgpr0 = COPY %2(s32)
49    SI_RETURN_TO_EPILOG implicit $vgpr0
50...
51
52---
53name:            test_and_and
54tracksRegLiveness: true
55body:             |
56  bb.0:
57    liveins: $vgpr0
58
59    ; CHECK-LABEL: name: test_and_and
60    ; CHECK: liveins: $vgpr0
61    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
62    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
63    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
64    ; CHECK: $vgpr0 = COPY [[AND]](s32)
65    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
66    %0:_(s32) = COPY $vgpr0
67    %1:_(s32) = G_CONSTANT i32 15
68    %2:_(s32) = G_CONSTANT i32 255
69    %3:_(s32) = G_AND %0, %1(s32)
70    %4:_(s32) = G_AND %3, %2
71    $vgpr0 = COPY %4(s32)
72    SI_RETURN_TO_EPILOG implicit $vgpr0
73...
74
75---
76name:            test_shl_and
77tracksRegLiveness: true
78body:             |
79  bb.0:
80    liveins: $sgpr0
81
82    ; CHECK-LABEL: name: test_shl_and
83    ; CHECK: liveins: $sgpr0
84    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
85    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
86    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
87    ; CHECK: $sgpr0 = COPY [[SHL]](s32)
88    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
89    %0:_(s32) = COPY $sgpr0
90    %1:_(s32) = G_CONSTANT i32 5
91    %2:_(s32) = G_CONSTANT i32 4294967264
92    %3:_(s32) = G_SHL %0, %1(s32)
93    %4:_(s32) = G_AND %3, %2
94    $sgpr0 = COPY %4(s32)
95    SI_RETURN_TO_EPILOG implicit $sgpr0
96...
97
98---
99name:            test_lshr_and
100tracksRegLiveness: true
101body:             |
102  bb.0:
103    liveins: $vgpr0
104
105    ; CHECK-LABEL: name: test_lshr_and
106    ; CHECK: liveins: $vgpr0
107    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
108    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
109    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
110    ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
111    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
112    %0:_(s32) = COPY $vgpr0
113    %1:_(s32) = G_CONSTANT i32 5
114    %2:_(s32) = G_CONSTANT i32 134217727
115    %3:_(s32) = G_LSHR %0, %1(s32)
116    %4:_(s32) = G_AND %3, %2
117    $vgpr0 = COPY %4(s32)
118    SI_RETURN_TO_EPILOG implicit $vgpr0
119...
120
121---
122name:            test_and_non_const
123tracksRegLiveness: true
124body:             |
125  bb.0:
126    liveins: $sgpr0, $sgpr1
127
128    ; CHECK-LABEL: name: test_and_non_const
129    ; CHECK: liveins: $sgpr0, $sgpr1
130    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
131    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
132    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
133    ; CHECK: $sgpr0 = COPY [[LSHR]](s32)
134    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
135    %0:_(s32) = COPY $sgpr0
136    %1:_(s32) = COPY $sgpr1
137    %2:_(s32) = G_CONSTANT i32 16
138    %3:_(s32) = G_CONSTANT i32 65535
139    %4:_(s32) = G_OR %1, %3
140    %5:_(s32) = G_LSHR %0, %2(s32)
141    %6:_(s32) = G_AND %5, %4
142    $sgpr0 = COPY %6(s32)
143    SI_RETURN_TO_EPILOG implicit $sgpr0
144...
145