1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
5
6# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+
7
8---
9name:            add_s16
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13
14body: |
15  bb.0:
16    liveins: $vgpr0, $vgpr1
17
18    ; GFX6-LABEL: name: add_s16
19    ; GFX6: liveins: $vgpr0, $vgpr1
20    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
22    ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
23    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
24    ; GFX10-LABEL: name: add_s16
25    ; GFX10: liveins: $vgpr0, $vgpr1
26    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
27    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
28    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
29    ; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
30    %0:vgpr(s32) = COPY $vgpr0
31    %1:vgpr(s32) = COPY $vgpr1
32    %2:vgpr(s16) = G_TRUNC %0
33    %3:vgpr(s16) = G_TRUNC %1
34    %4:vgpr(s16) = G_ADD %2, %3
35    S_ENDPGM 0, implicit %4
36
37...
38
39---
40name:            add_s16_zext_to_s32
41legalized:       true
42regBankSelected: true
43tracksRegLiveness: true
44
45body: |
46  bb.0:
47    liveins: $vgpr0, $vgpr1
48
49    ; GFX6-LABEL: name: add_s16_zext_to_s32
50    ; GFX6: liveins: $vgpr0, $vgpr1
51    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
52    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
53    ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
54    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
55    ; GFX10-LABEL: name: add_s16_zext_to_s32
56    ; GFX10: liveins: $vgpr0, $vgpr1
57    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
58    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
59    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
60    ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
61    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
62    %0:vgpr(s32) = COPY $vgpr0
63    %1:vgpr(s32) = COPY $vgpr1
64    %2:vgpr(s16) = G_TRUNC %0
65    %3:vgpr(s16) = G_TRUNC %1
66    %4:vgpr(s16) = G_ADD %2, %3
67    %5:vgpr(s32) = G_ZEXT %4
68    S_ENDPGM 0, implicit %5
69
70...
71
72---
73name:            add_s16_neg_inline_const_64
74legalized:       true
75regBankSelected: true
76tracksRegLiveness: true
77
78body: |
79  bb.0:
80    liveins: $vgpr0
81
82    ; GFX6-LABEL: name: add_s16_neg_inline_const_64
83    ; GFX6: liveins: $vgpr0
84    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
85    ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
86    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
87    ; GFX10-LABEL: name: add_s16_neg_inline_const_64
88    ; GFX10: liveins: $vgpr0
89    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
90    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
91    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
92    %0:vgpr(s32) = COPY $vgpr0
93    %1:vgpr(s16) = G_TRUNC %0
94    %2:vgpr(s16) = G_CONSTANT i16 -64
95    %3:vgpr(s16) = G_ADD %1, %2
96    S_ENDPGM 0, implicit %3
97
98...
99
100---
101name:            add_s16_neg_inline_const_64_zext_to_s32
102legalized:       true
103regBankSelected: true
104tracksRegLiveness: true
105
106body: |
107  bb.0:
108    liveins: $vgpr0
109
110    ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
111    ; GFX6: liveins: $vgpr0
112    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
113    ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
114    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
115    ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
116    ; GFX10: liveins: $vgpr0
117    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
118    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
119    ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
120    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
121    %0:vgpr(s32) = COPY $vgpr0
122    %1:vgpr(s16) = G_TRUNC %0
123    %2:vgpr(s16) = G_CONSTANT i16 -64
124    %3:vgpr(s16) = G_ADD %1, %2
125    %4:vgpr(s32) = G_ZEXT %3
126    S_ENDPGM 0, implicit %4
127
128...
129