1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE64 %s
3# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=WAVE32 %s
4
5---
6name: class_s32_vcc_sv
7legalized: true
8regBankSelected: true
9tracksRegLiveness: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $vgpr0
14    ; WAVE64-LABEL: name: class_s32_vcc_sv
15    ; WAVE64: liveins: $sgpr0, $vgpr0
16    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
19    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
20    ; WAVE32-LABEL: name: class_s32_vcc_sv
21    ; WAVE32: liveins: $sgpr0, $vgpr0
22    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
23    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
24    ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
25    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
26    %0:sgpr(s32) = COPY $sgpr0
27    %1:vgpr(s32) = COPY $vgpr0
28    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
29    S_ENDPGM 0, implicit %2
30...
31
32---
33name: class_s32_vcc_vs
34legalized: true
35regBankSelected: true
36tracksRegLiveness: true
37
38body: |
39  bb.0:
40    liveins: $sgpr0, $vgpr0
41    ; WAVE64-LABEL: name: class_s32_vcc_vs
42    ; WAVE64: liveins: $sgpr0, $vgpr0
43    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
44    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
45    ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
46    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
47    ; WAVE32-LABEL: name: class_s32_vcc_vs
48    ; WAVE32: liveins: $sgpr0, $vgpr0
49    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
50    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
51    ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
52    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
53    %0:vgpr(s32) = COPY $vgpr0
54    %1:sgpr(s32) = COPY $sgpr0
55    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
56    S_ENDPGM 0, implicit %2
57...
58
59---
60name: class_s32_vcc_vv
61legalized: true
62regBankSelected: true
63tracksRegLiveness: true
64
65body: |
66  bb.0:
67    liveins: $vgpr0, $vgpr1
68    ; WAVE64-LABEL: name: class_s32_vcc_vv
69    ; WAVE64: liveins: $vgpr0, $vgpr1
70    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
71    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
72    ; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
73    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
74    ; WAVE32-LABEL: name: class_s32_vcc_vv
75    ; WAVE32: liveins: $vgpr0, $vgpr1
76    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
77    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
78    ; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
79    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
80    %0:vgpr(s32) = COPY $vgpr0
81    %1:vgpr(s32) = COPY $vgpr1
82    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
83    S_ENDPGM 0, implicit %2
84...
85
86---
87name: class_s64_vcc_sv
88legalized: true
89regBankSelected: true
90tracksRegLiveness: true
91
92body: |
93  bb.0:
94    liveins: $sgpr0_sgpr1, $vgpr0
95    ; WAVE64-LABEL: name: class_s64_vcc_sv
96    ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
97    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
98    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
99    ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
100    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
101    ; WAVE32-LABEL: name: class_s64_vcc_sv
102    ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
103    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
104    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
105    ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
106    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
107    %0:sgpr(s64) = COPY $sgpr0_sgpr1
108    %1:vgpr(s32) = COPY $vgpr0
109    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
110    S_ENDPGM 0, implicit %2
111...
112
113---
114name: class_s64_vcc_vs
115legalized: true
116regBankSelected: true
117tracksRegLiveness: true
118
119body: |
120  bb.0:
121    liveins: $sgpr0_sgpr1, $vgpr0
122
123    ; WAVE64-LABEL: name: class_s64_vcc_vs
124    ; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
125    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
126    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
127    ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
128    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
129    ; WAVE32-LABEL: name: class_s64_vcc_vs
130    ; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
131    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
132    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
133    ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
134    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
135    %0:vgpr(s64) = COPY $vgpr0_vgpr1
136    %1:sgpr(s32) = COPY $sgpr0
137    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
138    S_ENDPGM 0, implicit %2
139...
140
141---
142name: class_s64_vcc_vv
143legalized: true
144regBankSelected: true
145tracksRegLiveness: true
146
147body: |
148  bb.0:
149    liveins: $vgpr0_vgpr1, $vgpr2
150
151    ; WAVE64-LABEL: name: class_s64_vcc_vv
152    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
153    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
154    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
155    ; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
156    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
157    ; WAVE32-LABEL: name: class_s64_vcc_vv
158    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
159    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
160    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
161    ; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
162    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
163    %0:vgpr(s64) = COPY $vgpr0_vgpr1
164    %1:vgpr(s32) = COPY $vgpr2
165    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
166    S_ENDPGM 0, implicit %2
167...
168