1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
3# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
4
5# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
6
7# SI-ERR-NOT: remark
8# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)
9# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)
10# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)
11# SI-ERR-NOT: remark
12
13---
14name: class_s16_vcc_sv
15legalized: true
16regBankSelected: true
17tracksRegLiveness: true
18
19body: |
20  bb.0:
21    liveins: $sgpr0, $vgpr0
22    ; WAVE32-LABEL: name: class_s16_vcc_sv
23    ; WAVE32: liveins: $sgpr0, $vgpr0
24    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
25    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26    ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
27    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
28    ; WAVE64-LABEL: name: class_s16_vcc_sv
29    ; WAVE64: liveins: $sgpr0, $vgpr0
30    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
31    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32    ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
33    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
34    %0:sgpr(s32) = COPY $sgpr0
35    %1:vgpr(s32) = COPY $vgpr0
36    %2:sgpr(s16) = G_TRUNC %0
37    %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
38    S_ENDPGM 0, implicit %4
39...
40
41---
42name: class_s16_vcc_vs
43legalized: true
44regBankSelected: true
45tracksRegLiveness: true
46
47body: |
48  bb.0:
49    liveins: $sgpr0, $vgpr0
50    ; WAVE32-LABEL: name: class_s16_vcc_vs
51    ; WAVE32: liveins: $sgpr0, $vgpr0
52    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
53    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
54    ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
55    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
56    ; WAVE64-LABEL: name: class_s16_vcc_vs
57    ; WAVE64: liveins: $sgpr0, $vgpr0
58    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
59    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
60    ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
61    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
62    %0:vgpr(s32) = COPY $vgpr0
63    %1:sgpr(s32) = COPY $sgpr0
64    %2:vgpr(s16) = G_TRUNC %0
65    %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
66    S_ENDPGM 0, implicit %4
67...
68
69---
70name: class_s16_vcc_vv
71legalized: true
72regBankSelected: true
73tracksRegLiveness: true
74
75body: |
76  bb.0:
77    liveins: $vgpr0, $vgpr1
78    ; WAVE32-LABEL: name: class_s16_vcc_vv
79    ; WAVE32: liveins: $vgpr0, $vgpr1
80    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
81    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
82    ; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
83    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
84    ; WAVE64-LABEL: name: class_s16_vcc_vv
85    ; WAVE64: liveins: $vgpr0, $vgpr1
86    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
87    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
88    ; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
89    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
90    %0:vgpr(s32) = COPY $vgpr0
91    %1:vgpr(s32) = COPY $vgpr1
92    %2:vgpr(s16) = G_TRUNC %0
93    %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
94    S_ENDPGM 0, implicit %4
95...
96