1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o - 2> %t | FileCheck -check-prefix=GCN %s
3# RUN: FileCheck -check-prefix=ERR %s < %t
4
5# ERR: remark: <unknown>:0:0: cannot select: %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %0:sgpr(s32) (in function: readfirstlane_s)
6
7---
8name: readfirstlane_v
9legalized: true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $vgpr0
16    ; GCN-LABEL: name: readfirstlane_v
17    ; GCN: liveins: $vgpr0
18    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec
20    ; GCN: S_ENDPGM 0, implicit [[V_READFIRSTLANE_B32_]]
21    %0:vgpr(s32) = COPY $vgpr0
22    %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %0
23    S_ENDPGM 0, implicit %1
24...
25
26---
27name: readfirstlane_v_imm
28legalized: true
29regBankSelected: true
30tracksRegLiveness: true
31
32body: |
33  bb.0:
34
35    ; GCN-LABEL: name: readfirstlane_v_imm
36    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
37    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY [[V_MOV_B32_e32_]]
38    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 [[COPY]]
39    ; GCN: S_ENDPGM 0, implicit [[S_MOV_B32_]]
40    %0:vgpr(s32) = G_CONSTANT i32 123
41    %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %0
42    S_ENDPGM 0, implicit %1
43...
44
45# Make sure this fails to select
46---
47name: readfirstlane_s
48legalized: true
49regBankSelected: true
50tracksRegLiveness: true
51
52body: |
53  bb.0:
54    liveins: $sgpr0
55    ; GCN-LABEL: name: readfirstlane_s
56    ; GCN: liveins: $sgpr0
57    ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
58    ; GCN: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
59    ; GCN: S_ENDPGM 0, implicit [[INT]](s32)
60    %0:sgpr(s32) = COPY $sgpr0
61    %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %0
62    S_ENDPGM 0, implicit %1
63...
64