1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
4# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
5
6---
7
8name:            and_s1_vcc_vcc_vcc
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $vgpr0, $vgpr1
16    ; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc
17    ; WAVE64: liveins: $vgpr0, $vgpr1
18    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
20    ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
21    ; WAVE64: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
22    ; WAVE64: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
23    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
24    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
25    ; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc
26    ; WAVE32: liveins: $vgpr0, $vgpr1
27    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
29    ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
30    ; WAVE32: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
31    ; WAVE32: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
32    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
33    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
34    %0:vgpr(s32) = COPY $vgpr0
35    %1:vgpr(s32) = COPY $vgpr1
36    %2:vgpr(s32) = G_CONSTANT i32 0
37    %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
38    %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
39    %5:vcc(s1) = G_AND %3, %4
40    S_ENDPGM 0, implicit %5
41...
42
43# Should fail to select
44---
45
46name:            and_s1_sgpr_sgpr_sgpr
47legalized:       true
48regBankSelected: true
49tracksRegLiveness: true
50
51body: |
52  bb.0:
53    liveins: $sgpr0, $sgpr1
54    ; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr
55    ; WAVE64: liveins: $sgpr0, $sgpr1
56    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
57    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
58    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
59    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
60    ; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr
61    ; WAVE32: liveins: $sgpr0, $sgpr1
62    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
63    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
64    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
65    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
66    %0:sgpr(s32) = COPY $sgpr0
67    %1:sgpr(s32) = COPY $sgpr1
68    %2:sgpr(s1) = G_TRUNC %0
69    %3:sgpr(s1) = G_TRUNC %1
70    %4:sgpr(s1) = G_AND %2, %3
71    S_ENDPGM 0, implicit %4
72...
73
74---
75
76name:            and_s16_sgpr_sgpr_sgpr
77legalized:       true
78regBankSelected: true
79tracksRegLiveness: true
80
81body: |
82  bb.0:
83    liveins: $sgpr0, $sgpr1
84    ; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr
85    ; WAVE64: liveins: $sgpr0, $sgpr1
86    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
87    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
88    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
89    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
90    ; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr
91    ; WAVE32: liveins: $sgpr0, $sgpr1
92    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
93    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
94    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
95    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
96    %0:sgpr(s32) = COPY $sgpr0
97    %1:sgpr(s32) = COPY $sgpr1
98    %2:sgpr(s16) = G_TRUNC %0
99    %3:sgpr(s16) = G_TRUNC %1
100    %4:sgpr(s16) = G_AND %2, %3
101    S_ENDPGM 0, implicit %4
102...
103
104---
105
106name:            and_s16_vgpr_vgpr_vgpr
107legalized:       true
108regBankSelected: true
109tracksRegLiveness: true
110
111body: |
112  bb.0:
113    liveins: $vgpr0, $vgpr1
114    ; WAVE64-LABEL: name: and_s16_vgpr_vgpr_vgpr
115    ; WAVE64: liveins: $vgpr0, $vgpr1
116    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
117    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
118    ; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
119    ; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
120    ; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr
121    ; WAVE32: liveins: $vgpr0, $vgpr1
122    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
123    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
124    ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
125    ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
126    %0:vgpr(s32) = COPY $vgpr0
127    %1:vgpr(s32) = COPY $vgpr1
128    %2:vgpr(s16) = G_TRUNC %0
129    %3:vgpr(s16) = G_TRUNC %1
130    %4:vgpr(s16) = G_AND %2, %3
131    S_ENDPGM 0, implicit %4
132...
133
134---
135
136name:            and_s32_sgpr_sgpr_sgpr
137legalized:       true
138regBankSelected: true
139tracksRegLiveness: true
140
141body: |
142  bb.0:
143    liveins: $sgpr0, $sgpr1
144    ; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr
145    ; WAVE64: liveins: $sgpr0, $sgpr1
146    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
147    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
148    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
149    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
150    ; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr
151    ; WAVE32: liveins: $sgpr0, $sgpr1
152    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
153    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
154    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
155    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
156    %0:sgpr(s32) = COPY $sgpr0
157    %1:sgpr(s32) = COPY $sgpr1
158    %2:sgpr(s32) = G_AND %0, %1
159    S_ENDPGM 0, implicit %2
160...
161
162---
163
164name:            and_s64_sgpr_sgpr_sgpr
165legalized:       true
166regBankSelected: true
167tracksRegLiveness: true
168
169body: |
170  bb.0:
171    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
172    ; WAVE64-LABEL: name: and_s64_sgpr_sgpr_sgpr
173    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
174    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
175    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
176    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def $scc
177    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
178    ; WAVE32-LABEL: name: and_s64_sgpr_sgpr_sgpr
179    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
180    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
181    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
182    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def $scc
183    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
184    %0:sgpr(s64) = COPY $sgpr0_sgpr1
185    %1:sgpr(s64) = COPY $sgpr2_sgpr3
186    %2:sgpr(s64) = G_AND %0, %1
187    S_ENDPGM 0, implicit %2
188...
189
190---
191
192name:            and_v2s16_sgpr_sgpr_sgpr
193legalized:       true
194regBankSelected: true
195tracksRegLiveness: true
196
197body: |
198  bb.0:
199    liveins: $sgpr0, $sgpr1
200    ; WAVE64-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
201    ; WAVE64: liveins: $sgpr0, $sgpr1
202    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
203    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
204    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
205    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
206    ; WAVE32-LABEL: name: and_v2s16_sgpr_sgpr_sgpr
207    ; WAVE32: liveins: $sgpr0, $sgpr1
208    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
209    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
210    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
211    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
212    %0:sgpr(<2 x s16>) = COPY $sgpr0
213    %1:sgpr(<2 x s16>) = COPY $sgpr1
214    %2:sgpr(<2 x s16>) = G_AND %0, %1
215    S_ENDPGM 0, implicit %2
216...
217
218---
219
220name:            and_v2s32_sgpr_sgpr_sgpr
221legalized:       true
222regBankSelected: true
223tracksRegLiveness: true
224
225body: |
226  bb.0:
227    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
228    ; WAVE64-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
229    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
230    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
231    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
232    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
233    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
234    ; WAVE32-LABEL: name: and_v2s32_sgpr_sgpr_sgpr
235    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
236    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
237    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
238    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
239    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
240    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
241    %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
242    %2:sgpr(<2 x s32>) = G_AND %0, %1
243    S_ENDPGM 0, implicit %2
244...
245
246---
247
248name:            and_v4s16_sgpr_sgpr_sgpr
249legalized:       true
250regBankSelected: true
251tracksRegLiveness: true
252
253body: |
254  bb.0:
255    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
256    ; WAVE64-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
257    ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
258    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
259    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
260    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
261    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
262    ; WAVE32-LABEL: name: and_v4s16_sgpr_sgpr_sgpr
263    ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
264    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
265    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
266    ; WAVE32: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
267    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B64_]]
268    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
269    %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
270    %2:sgpr(<4 x s16>) = G_AND %0, %1
271    S_ENDPGM 0, implicit %2
272...
273
274---
275
276name:            and_s32_vgpr_vgpr_vgpr
277legalized:       true
278regBankSelected: true
279tracksRegLiveness: true
280
281body: |
282  bb.0:
283    liveins: $vgpr0, $vgpr1
284    ; WAVE64-LABEL: name: and_s32_vgpr_vgpr_vgpr
285    ; WAVE64: liveins: $vgpr0, $vgpr1
286    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
287    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
288    ; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
289    ; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
290    ; WAVE32-LABEL: name: and_s32_vgpr_vgpr_vgpr
291    ; WAVE32: liveins: $vgpr0, $vgpr1
292    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
293    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
294    ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
295    ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
296    %0:vgpr(s32) = COPY $vgpr0
297    %1:vgpr(s32) = COPY $vgpr1
298    %2:vgpr(s32) = G_AND %0, %1
299    S_ENDPGM 0, implicit %2
300...
301
302---
303
304name:            and_v2s16_vgpr_vgpr_vgpr
305legalized:       true
306regBankSelected: true
307tracksRegLiveness: true
308
309body: |
310  bb.0:
311    liveins: $vgpr0, $vgpr1
312    ; WAVE64-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
313    ; WAVE64: liveins: $vgpr0, $vgpr1
314    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
315    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
316    ; WAVE64: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
317    ; WAVE64: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
318    ; WAVE32-LABEL: name: and_v2s16_vgpr_vgpr_vgpr
319    ; WAVE32: liveins: $vgpr0, $vgpr1
320    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
321    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
322    ; WAVE32: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
323    ; WAVE32: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]
324    %0:vgpr(<2 x s16>) = COPY $vgpr0
325    %1:vgpr(<2 x s16>) = COPY $vgpr1
326    %2:vgpr(<2 x s16>) = G_AND %0, %1
327    S_ENDPGM 0, implicit %2
328...
329
330
331# This should fail to select
332---
333
334name:            and_s64_vgpr_vgpr_vgpr
335legalized:       true
336regBankSelected: true
337tracksRegLiveness: true
338
339body: |
340  bb.0:
341    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
342    ; WAVE64-LABEL: name: and_s64_vgpr_vgpr_vgpr
343    ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
344    ; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
345    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
346    ; WAVE64: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
347    ; WAVE64: S_ENDPGM 0, implicit [[AND]](s64)
348    ; WAVE32-LABEL: name: and_s64_vgpr_vgpr_vgpr
349    ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
350    ; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
351    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
352    ; WAVE32: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]
353    ; WAVE32: S_ENDPGM 0, implicit [[AND]](s64)
354    %0:vgpr(s64) = COPY $vgpr0_vgpr1
355    %1:vgpr(s64) = COPY $vgpr2_vgpr3
356    %2:vgpr(s64) = G_AND %0, %1
357    S_ENDPGM 0, implicit %2
358...
359
360---
361
362name:            and_s1_vcc_copy_to_vcc
363legalized:       true
364regBankSelected: true
365tracksRegLiveness: true
366
367body: |
368  bb.0:
369    liveins: $vgpr0, $vgpr1
370    ; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc
371    ; WAVE64: liveins: $vgpr0, $vgpr1
372    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
373    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
374    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
375    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
376    ; WAVE64: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
377    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
378    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
379    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B64_]]
380    ; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc
381    ; WAVE32: liveins: $vgpr0, $vgpr1
382    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
383    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
384    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
385    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
386    ; WAVE32: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
387    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
388    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
389    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
390    %0:vgpr(s32) = COPY $vgpr0
391    %1:vgpr(s32) = COPY $vgpr1
392    %2:vgpr(s1) = G_TRUNC %0
393    %3:vgpr(s1) = G_TRUNC %1
394    %4:vcc(s1) = COPY %2
395    %5:vcc(s1) = COPY %3
396    %6:vcc(s1) = G_AND %4, %5
397    S_ENDPGM 0, implicit %6
398...
399
400# The selector for the copy of the and result may constrain the result
401# register of the and, losing that it is a VCCRegBank context.
402
403# Works for wave32, should fail for wave64
404---
405name:            copy_select_constrain_vcc_result_reg_wave32
406legalized:       true
407regBankSelected: true
408tracksRegLiveness: true
409body:             |
410  bb.0:
411    liveins: $vgpr0, $sgpr0
412
413    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
414    ; WAVE64: liveins: $vgpr0, $sgpr0
415    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
416    ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
417    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
418    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
419    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
420    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
421    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
422    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]]
423    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
424    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
425    ; WAVE32: liveins: $vgpr0, $sgpr0
426    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
427    ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
428    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
429    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
430    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
431    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
432    ; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
433    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]
434    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
435    %1:vgpr(s32) = COPY $vgpr0
436    %0:vgpr(s1) = G_TRUNC %1(s32)
437    %sgpr0:sgpr(s32) = COPY $sgpr0
438    %2:sgpr(s1) = G_TRUNC %sgpr0
439    %6:sgpr(s32) = G_CONSTANT i32 0
440    %7:sgpr(p1) = G_IMPLICIT_DEF
441    %9:vcc(s1) = COPY %0(s1)
442    %10:vcc(s1) = COPY %2(s1)
443    %8:vcc(s1) = G_AND %9, %10
444    %3:sreg_32_xm0(s1) = COPY %8(s1)
445    S_ENDPGM 0, implicit %3
446
447...
448
449# Works for wave64, should fail for wave32
450---
451name:            copy_select_constrain_vcc_result_reg_wave64
452legalized:       true
453regBankSelected: true
454tracksRegLiveness: true
455body:             |
456  bb.0:
457    liveins: $vgpr0, $sgpr0
458
459    ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
460    ; WAVE64: liveins: $vgpr0, $sgpr0
461    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
462    ; WAVE64: %sgpr0:sreg_32 = COPY $sgpr0
463    ; WAVE64: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
464    ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
465    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
466    ; WAVE64: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
467    ; WAVE64: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
468    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B64_]]
469    ; WAVE64: S_ENDPGM 0, implicit [[COPY1]]
470    ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
471    ; WAVE32: liveins: $vgpr0, $sgpr0
472    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
473    ; WAVE32: %sgpr0:sreg_32 = COPY $sgpr0
474    ; WAVE32: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
475    ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
476    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def $scc
477    ; WAVE32: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
478    ; WAVE32: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
479    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]]
480    ; WAVE32: S_ENDPGM 0, implicit [[COPY1]]
481    %1:vgpr(s32) = COPY $vgpr0
482    %0:vgpr(s1) = G_TRUNC %1(s32)
483    %sgpr0:sgpr(s32) = COPY $sgpr0
484    %2:sgpr(s1) = G_TRUNC %sgpr0
485    %6:sgpr(s32) = G_CONSTANT i32 0
486    %7:sgpr(p1) = G_IMPLICIT_DEF
487    %9:vcc(s1) = COPY %0(s1)
488    %10:vcc(s1) = COPY %2(s1)
489    %8:vcc(s1) = G_AND %9, %10
490    %3:sreg_64_xexec(s1) = COPY %8(s1)
491    S_ENDPGM 0, implicit %3
492
493...
494
495---
496
497name:            and_s32_sgpr_sgpr_sgpr_result_reg_class
498legalized:       true
499regBankSelected: true
500tracksRegLiveness: true
501
502body: |
503  bb.0:
504    liveins: $sgpr0, $sgpr1
505    ; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class
506    ; WAVE64: liveins: $sgpr0, $sgpr1
507    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
508    ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
509    ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
510    ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
511    ; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class
512    ; WAVE32: liveins: $sgpr0, $sgpr1
513    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
514    ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
515    ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
516    ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
517    %0:sgpr(s32) = COPY $sgpr0
518    %1:sgpr(s32) = COPY $sgpr1
519    %2:sreg_32(s32) = G_AND %0, %1
520    S_ENDPGM 0, implicit %2
521...
522