1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s 3 4--- 5name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0, $sgpr1 13 14 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_s32 15 ; GFX9: liveins: $sgpr0, $sgpr1 16 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 17 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 18 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[COPY1]] 19 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 20 %0:sgpr(s32) = COPY $sgpr0 21 %1:sgpr(s32) = COPY $sgpr1 22 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 23 S_ENDPGM 0, implicit %2 24... 25 26--- 27name: test_build_vector_trunc_s_pack_lh 28legalized: true 29regBankSelected: true 30tracksRegLiveness: true 31 32body: | 33 bb.0: 34 liveins: $sgpr0, $sgpr1 35 36 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh 37 ; GFX9: liveins: $sgpr0, $sgpr1 38 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 39 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 40 ; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[COPY]], [[COPY1]] 41 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]] 42 %0:sgpr(s32) = COPY $sgpr0 43 %1:sgpr(s32) = COPY $sgpr1 44 %2:sgpr(s32) = G_CONSTANT i32 16 45 %3:sgpr(s32) = G_LSHR %1, %2 46 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 47 S_ENDPGM 0, implicit %4 48... 49 50# There is no s_pack_hl_b32 51--- 52name: test_build_vector_trunc_s_pack_lh_swapped 53legalized: true 54regBankSelected: true 55tracksRegLiveness: true 56 57body: | 58 bb.0: 59 liveins: $sgpr0, $sgpr1 60 61 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_swapped 62 ; GFX9: liveins: $sgpr0, $sgpr1 63 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 64 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 65 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 66 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc 67 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[COPY]] 68 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 69 %0:sgpr(s32) = COPY $sgpr0 70 %1:sgpr(s32) = COPY $sgpr1 71 %2:sgpr(s32) = G_CONSTANT i32 16 72 %3:sgpr(s32) = G_LSHR %1, %2 73 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 74 S_ENDPGM 0, implicit %4 75... 76 77--- 78name: test_build_vector_trunc_s_pack_hh 79legalized: true 80regBankSelected: true 81tracksRegLiveness: true 82 83body: | 84 bb.0: 85 liveins: $sgpr0, $sgpr1 86 87 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh 88 ; GFX9: liveins: $sgpr0, $sgpr1 89 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 90 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 91 ; GFX9: [[S_PACK_HH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_HH_B32_B16 [[COPY]], [[COPY1]] 92 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]] 93 %0:sgpr(s32) = COPY $sgpr0 94 %1:sgpr(s32) = COPY $sgpr1 95 %2:sgpr(s32) = G_CONSTANT i32 16 96 %3:sgpr(s32) = G_LSHR %0, %2 97 %4:sgpr(s32) = G_LSHR %1, %2 98 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 99 S_ENDPGM 0, implicit %5 100... 101 102# TODO: Should this use an and instead? 103--- 104name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 105legalized: true 106regBankSelected: true 107tracksRegLiveness: true 108 109body: | 110 bb.0: 111 liveins: $sgpr0 112 113 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_0_s32 114 ; GFX9: liveins: $sgpr0 115 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 116 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 117 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 118 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 119 %0:sgpr(s32) = COPY $sgpr0 120 %1:sgpr(s32) = G_CONSTANT i32 0 121 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 122 S_ENDPGM 0, implicit %2 123... 124 125--- 126name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 127legalized: true 128regBankSelected: true 129tracksRegLiveness: true 130 131body: | 132 bb.0: 133 liveins: $sgpr0 134 135 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_0_s32_s_s32 136 ; GFX9: liveins: $sgpr0 137 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 138 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 139 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 140 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 141 %0:sgpr(s32) = COPY $sgpr0 142 %1:sgpr(s32) = G_CONSTANT i32 0 143 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 144 S_ENDPGM 0, implicit %2 145... 146 147--- 148name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 149legalized: true 150regBankSelected: true 151tracksRegLiveness: true 152 153body: | 154 bb.0: 155 liveins: $sgpr0 156 157 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_s_undef_s32 158 ; GFX9: liveins: $sgpr0 159 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 160 ; GFX9: S_ENDPGM 0, implicit [[COPY]] 161 %0:sgpr(s32) = COPY $sgpr0 162 %1:sgpr(s32) = G_IMPLICIT_DEF 163 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 164 S_ENDPGM 0, implicit %2 165... 166 167--- 168name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 169legalized: true 170regBankSelected: true 171tracksRegLiveness: true 172 173body: | 174 bb.0: 175 liveins: $sgpr0 176 177 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s32_s_s32 178 ; GFX9: liveins: $sgpr0 179 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 180 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 181 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] 182 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 183 %0:sgpr(s32) = COPY $sgpr0 184 %1:sgpr(s32) = G_IMPLICIT_DEF 185 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0 186 S_ENDPGM 0, implicit %2 187... 188 189--- 190name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 191legalized: true 192regBankSelected: true 193tracksRegLiveness: true 194 195body: | 196 bb.0: 197 liveins: $sgpr1 198 199 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_undef_s_s32 200 ; GFX9: liveins: $sgpr1 201 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 202 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 203 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]] 204 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 205 %0:sgpr(s32) = G_IMPLICIT_DEF 206 %1:sgpr(s32) = COPY $sgpr1 207 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 208 S_ENDPGM 0, implicit %2 209... 210 211--- 212name: test_build_vector_trunc_s_v2s16_s_s32_undef 213legalized: true 214regBankSelected: true 215tracksRegLiveness: true 216 217body: | 218 bb.0: 219 liveins: $sgpr0 220 221 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_undef 222 ; GFX9: liveins: $sgpr0 223 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 224 ; GFX9: S_ENDPGM 0, implicit [[COPY]] 225 %0:sgpr(s32) = COPY $sgpr0 226 %1:sgpr(s32) = G_IMPLICIT_DEF 227 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 228 S_ENDPGM 0, implicit %2 229... 230 231--- 232name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 233legalized: true 234regBankSelected: true 235tracksRegLiveness: true 236 237body: | 238 bb.0: 239 liveins: $sgpr1 240 241 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_zero_s_s32 242 ; GFX9: liveins: $sgpr1 243 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 244 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr1 245 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 246 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 247 %0:sgpr(s32) = G_CONSTANT i32 0 248 %1:sgpr(s32) = COPY $sgpr1 249 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 250 S_ENDPGM 0, implicit %2 251... 252 253--- 254name: test_build_vector_trunc_s_v2s16_s_s32_zero 255legalized: true 256regBankSelected: true 257tracksRegLiveness: true 258 259body: | 260 bb.0: 261 liveins: $sgpr0 262 263 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_s_s32_zero 264 ; GFX9: liveins: $sgpr0 265 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 266 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 267 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 268 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 269 %0:sgpr(s32) = COPY $sgpr0 270 %1:sgpr(s32) = G_CONSTANT i32 0 271 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 272 S_ENDPGM 0, implicit %2 273... 274 275--- 276name: test_build_vector_trunc_lshr16_zero 277legalized: true 278regBankSelected: true 279tracksRegLiveness: true 280 281body: | 282 bb.0: 283 liveins: $sgpr0 284 285 ; GFX9-LABEL: name: test_build_vector_trunc_lshr16_zero 286 ; GFX9: liveins: $sgpr0 287 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 288 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], 16, implicit-def $scc 289 ; GFX9: S_ENDPGM 0, implicit [[S_LSHR_B32_]] 290 %0:sgpr(s32) = G_CONSTANT i32 0 291 %1:sgpr(s32) = COPY $sgpr0 292 %2:sgpr(s32) = G_CONSTANT i32 16 293 %3:sgpr(s32) = G_LSHR %1, %2 294 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0 295 S_ENDPGM 0, implicit %4 296... 297 298# Don't use pack since it would duplicate the shift use 299--- 300name: test_build_vector_trunc_s_pack_lh_multi_use 301legalized: true 302regBankSelected: true 303tracksRegLiveness: true 304 305body: | 306 bb.0: 307 liveins: $sgpr0, $sgpr1 308 309 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use 310 ; GFX9: liveins: $sgpr0, $sgpr1 311 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 312 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 313 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 314 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc 315 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] 316 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]] 317 %0:sgpr(s32) = COPY $sgpr0 318 %1:sgpr(s32) = COPY $sgpr1 319 %2:sgpr(s32) = G_CONSTANT i32 16 320 %3:sgpr(s32) = G_LSHR %1, %2 321 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 322 S_ENDPGM 0, implicit %4, implicit %3 323... 324 325--- 326name: test_build_vector_trunc_s_pack_hh_multi_use_lhs 327legalized: true 328regBankSelected: true 329tracksRegLiveness: true 330 331body: | 332 bb.0: 333 liveins: $sgpr0, $sgpr1 334 335 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs 336 ; GFX9: liveins: $sgpr0, $sgpr1 337 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 338 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 339 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 340 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc 341 ; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]] 342 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]] 343 %0:sgpr(s32) = COPY $sgpr0 344 %1:sgpr(s32) = COPY $sgpr1 345 %2:sgpr(s32) = G_CONSTANT i32 16 346 %3:sgpr(s32) = G_LSHR %0, %2 347 %4:sgpr(s32) = G_LSHR %1, %2 348 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 349 S_ENDPGM 0, implicit %5, implicit %3 350... 351 352--- 353name: test_build_vector_trunc_s_pack_hh_multi_use_rhs 354legalized: true 355regBankSelected: true 356tracksRegLiveness: true 357 358body: | 359 bb.0: 360 liveins: $sgpr0, $sgpr1 361 362 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs 363 ; GFX9: liveins: $sgpr0, $sgpr1 364 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 365 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 366 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 367 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc 368 ; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc 369 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] 370 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]] 371 %0:sgpr(s32) = COPY $sgpr0 372 %1:sgpr(s32) = COPY $sgpr1 373 %2:sgpr(s32) = G_CONSTANT i32 16 374 %3:sgpr(s32) = G_LSHR %0, %2 375 %4:sgpr(s32) = G_LSHR %1, %2 376 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 377 S_ENDPGM 0, implicit %5, implicit %4 378... 379 380--- 381name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt 382legalized: true 383regBankSelected: true 384tracksRegLiveness: true 385 386body: | 387 bb.0: 388 liveins: $sgpr0, $sgpr1 389 390 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt 391 ; GFX9: liveins: $sgpr0, $sgpr1 392 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 393 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 394 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 395 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc 396 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]] 397 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 398 %0:sgpr(s32) = COPY $sgpr0 399 %1:sgpr(s32) = COPY $sgpr1 400 %2:sgpr(s32) = G_CONSTANT i32 15 401 %3:sgpr(s32) = G_LSHR %1, %2 402 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3 403 S_ENDPGM 0, implicit %4 404... 405 406--- 407name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt 408legalized: true 409regBankSelected: true 410tracksRegLiveness: true 411 412body: | 413 bb.0: 414 liveins: $sgpr0, $sgpr1 415 416 ; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt 417 ; GFX9: liveins: $sgpr0, $sgpr1 418 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 419 ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 420 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15 421 ; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc 422 ; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc 423 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]] 424 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 425 %0:sgpr(s32) = COPY $sgpr0 426 %1:sgpr(s32) = COPY $sgpr1 427 %2:sgpr(s32) = G_CONSTANT i32 15 428 %3:sgpr(s32) = G_LSHR %0, %2 429 %4:sgpr(s32) = G_LSHR %1, %2 430 %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4 431 S_ENDPGM 0, implicit %5 432... 433 434--- 435name: test_build_vector_trunc_s_v2s16_constant_constant 436legalized: true 437regBankSelected: true 438tracksRegLiveness: true 439 440body: | 441 bb.0: 442 443 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_constant 444 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 445 ; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]] 446 %0:sgpr(s32) = G_CONSTANT i32 123 447 %1:sgpr(s32) = G_CONSTANT i32 456 448 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 449 S_ENDPGM 0, implicit %2 450... 451 452--- 453name: test_build_vector_trunc_s_v2s16_constant_impdef 454legalized: true 455regBankSelected: true 456tracksRegLiveness: true 457 458body: | 459 bb.0: 460 461 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_impdef 462 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 463 ; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]] 464 %0:sgpr(s32) = G_CONSTANT i32 123 465 %1:sgpr(s32) = G_IMPLICIT_DEF 466 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 467 S_ENDPGM 0, implicit %2 468... 469 470--- 471name: test_build_vector_trunc_s_v2s16_impdef_constant 472legalized: true 473regBankSelected: true 474tracksRegLiveness: true 475 476body: | 477 bb.0: 478 479 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_constant 480 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 481 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 482 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] 483 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 484 %0:sgpr(s32) = G_IMPLICIT_DEF 485 %1:sgpr(s32) = G_CONSTANT i32 123 486 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 487 S_ENDPGM 0, implicit %2 488... 489 490--- 491name: test_build_vector_trunc_s_v2s16_impdef_impdef 492legalized: true 493regBankSelected: true 494tracksRegLiveness: true 495 496body: | 497 bb.0: 498 499 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_impdef_impdef 500 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 501 ; GFX9: S_ENDPGM 0, implicit [[DEF]] 502 %0:sgpr(s32) = G_IMPLICIT_DEF 503 %1:sgpr(s32) = G_IMPLICIT_DEF 504 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 505 S_ENDPGM 0, implicit %2 506... 507 508--- 509name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant 510legalized: true 511regBankSelected: true 512tracksRegLiveness: true 513 514body: | 515 bb.0: 516 517 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_constant_zext_constant 518 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 29884539 519 ; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]] 520 %0:sgpr(s16) = G_CONSTANT i16 123 521 %1:sgpr(s16) = G_CONSTANT i16 456 522 %2:sgpr(s32) = G_ZEXT %0 523 %3:sgpr(s32) = G_ZEXT %1 524 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 525 S_ENDPGM 0, implicit %4 526... 527 528--- 529name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant 530legalized: true 531regBankSelected: true 532tracksRegLiveness: true 533 534body: | 535 bb.0: 536 537 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_zext_impdef_zext_constant 538 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 539 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 540 ; GFX9: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[DEF]], 1048576, implicit-def $scc 541 ; GFX9: [[S_BFE_U32_1:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_MOV_B32_]], 1048576, implicit-def $scc 542 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_BFE_U32_]], [[S_BFE_U32_1]] 543 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 544 %0:sgpr(s16) = G_IMPLICIT_DEF 545 %1:sgpr(s16) = G_CONSTANT i16 123 546 %2:sgpr(s32) = G_ZEXT %0 547 %3:sgpr(s32) = G_ZEXT %1 548 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 549 S_ENDPGM 0, implicit %4 550... 551 552--- 553name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant 554legalized: true 555regBankSelected: true 556tracksRegLiveness: true 557 558body: | 559 bb.0: 560 561 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_sext_constant_sext_constant 562 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4294836208 563 ; GFX9: S_ENDPGM 0, implicit [[S_MOV_B32_]] 564 %0:sgpr(s16) = G_CONSTANT i16 -16 565 %1:sgpr(s16) = G_CONSTANT i16 -3 566 %2:sgpr(s32) = G_SEXT %0 567 %3:sgpr(s32) = G_SEXT %1 568 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 569 S_ENDPGM 0, implicit %4 570... 571 572--- 573name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant 574legalized: true 575regBankSelected: true 576tracksRegLiveness: true 577 578body: | 579 bb.0: 580 581 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_constant_anyext_constant 582 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 583 ; GFX9: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 456 584 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[S_MOV_B32_1]] 585 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 586 %0:sgpr(s16) = G_CONSTANT i16 123 587 %1:sgpr(s16) = G_CONSTANT i16 456 588 %2:sgpr(s32) = G_ANYEXT %0 589 %3:sgpr(s32) = G_ANYEXT %1 590 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 591 S_ENDPGM 0, implicit %4 592... 593 594--- 595name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant 596legalized: true 597regBankSelected: true 598tracksRegLiveness: true 599 600body: | 601 bb.0: 602 603 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_anyext_impdef_anyext_constant 604 ; GFX9: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF 605 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123 606 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[S_MOV_B32_]] 607 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 608 %0:sgpr(s16) = G_IMPLICIT_DEF 609 %1:sgpr(s16) = G_CONSTANT i16 123 610 %2:sgpr(s32) = G_ANYEXT %0 611 %3:sgpr(s32) = G_ANYEXT %1 612 %4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %2, %3 613 S_ENDPGM 0, implicit %4 614... 615 616--- 617name: test_build_vector_trunc_s_v2s16_var_constant 618legalized: true 619regBankSelected: true 620tracksRegLiveness: true 621 622body: | 623 bb.0: 624 liveins: $sgpr0 625 626 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_constant 627 ; GFX9: liveins: $sgpr0 628 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 629 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 630 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 631 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 632 %0:sgpr(s32) = COPY $sgpr0 633 %1:sgpr(s32) = G_CONSTANT i32 456 634 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 635 S_ENDPGM 0, implicit %2 636... 637 638--- 639name: test_build_vector_trunc_s_v2s16_constant_var 640legalized: true 641regBankSelected: true 642tracksRegLiveness: true 643 644body: | 645 bb.0: 646 liveins: $sgpr0 647 648 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_constant_var 649 ; GFX9: liveins: $sgpr0 650 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 456 651 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 652 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 653 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 654 %0:sgpr(s32) = G_CONSTANT i32 456 655 %1:sgpr(s32) = COPY $sgpr0 656 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 657 S_ENDPGM 0, implicit %2 658... 659 660--- 661name: test_build_vector_trunc_s_v2s16_var_0 662legalized: true 663regBankSelected: true 664tracksRegLiveness: true 665 666body: | 667 bb.0: 668 liveins: $sgpr0 669 670 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_var_0 671 ; GFX9: liveins: $sgpr0 672 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 673 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 674 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_MOV_B32_]] 675 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 676 %0:sgpr(s32) = COPY $sgpr0 677 %1:sgpr(s32) = G_CONSTANT i32 0 678 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 679 S_ENDPGM 0, implicit %2 680... 681 682--- 683name: test_build_vector_trunc_s_v2s16_0_var 684legalized: true 685regBankSelected: true 686tracksRegLiveness: true 687 688body: | 689 bb.0: 690 liveins: $sgpr0 691 692 ; GFX9-LABEL: name: test_build_vector_trunc_s_v2s16_0_var 693 ; GFX9: liveins: $sgpr0 694 ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 695 ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 696 ; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]] 697 ; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]] 698 %0:sgpr(s32) = G_CONSTANT i32 0 699 %1:sgpr(s32) = COPY $sgpr0 700 %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1 701 S_ENDPGM 0, implicit %2 702... 703