1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: fexp2_s32_vs
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $sgpr0
13
14    ; CHECK-LABEL: name: fexp2_s32_vs
15    ; CHECK: liveins: $sgpr0
16    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17    ; CHECK: %1:vgpr_32 = nofpexcept V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
18    ; CHECK: S_ENDPGM 0, implicit %1
19    %0:sgpr(s32) = COPY $sgpr0
20    %1:vgpr(s32) = G_FEXP2 %0
21    S_ENDPGM 0, implicit %1
22...
23
24---
25name: fexp2_s32_vv
26legalized: true
27regBankSelected: true
28tracksRegLiveness: true
29
30body: |
31  bb.0:
32    liveins: $vgpr0
33
34    ; CHECK-LABEL: name: fexp2_s32_vv
35    ; CHECK: liveins: $vgpr0
36    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
37    ; CHECK: %1:vgpr_32 = nofpexcept V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
38    ; CHECK: S_ENDPGM 0, implicit %1
39    %0:vgpr(s32) = COPY $vgpr0
40    %1:vgpr(s32) = G_FEXP2 %0
41    S_ENDPGM 0, implicit %1
42...
43