1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
5
6---
7
8name:            and_or_s32_sgpr_sgpr_sgpr
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $sgpr0, $sgpr1, $sgpr2
16    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
17    ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
18    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
20    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
21    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
22    ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
23    ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
24    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
25    ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
26    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
27    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
28    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
29    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
30    ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
31    ; GFX9: S_ENDPGM 0, implicit [[S_OR_B32_]]
32    ; GFX10-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
33    ; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
34    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
35    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
36    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
37    ; GFX10: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
38    ; GFX10: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
39    ; GFX10: S_ENDPGM 0, implicit [[S_OR_B32_]]
40    %0:sgpr(s32) = COPY $sgpr0
41    %1:sgpr(s32) = COPY $sgpr1
42    %2:sgpr(s32) = COPY $sgpr2
43    %3:sgpr(s32) = G_AND %0, %1
44    %4:sgpr(s32) = G_OR %3, %2
45    S_ENDPGM 0, implicit %4
46...
47
48---
49
50name:            and_or_s32_vgpr_vgpr_vgpr
51legalized:       true
52regBankSelected: true
53tracksRegLiveness: true
54
55body: |
56  bb.0:
57    liveins: $vgpr0, $vgpr1, $vgpr2
58    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
59    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
60    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
61    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
62    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
63    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
64    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[COPY2]], implicit $exec
65    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
66    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
67    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
68    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
69    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
70    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
71    ; GFX9: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
72    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
73    ; GFX10-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
74    ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
75    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
76    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
77    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
78    ; GFX10: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
79    ; GFX10: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
80    %0:vgpr(s32) = COPY $vgpr0
81    %1:vgpr(s32) = COPY $vgpr1
82    %2:vgpr(s32) = COPY $vgpr2
83    %3:vgpr(s32) = G_AND %0, %1
84    %4:vgpr(s32) = G_OR %3, %2
85    S_ENDPGM 0, implicit %4
86...
87
88---
89
90name:            and_or_s32_vgpr_vgpr_vgpr_commute
91legalized:       true
92regBankSelected: true
93tracksRegLiveness: true
94
95body: |
96  bb.0:
97    liveins: $vgpr0, $vgpr1, $vgpr2
98    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
99    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
100    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
101    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
102    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
103    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
104    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY2]], [[V_AND_B32_e64_]], implicit $exec
105    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
106    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
107    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
108    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
109    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
110    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
111    ; GFX9: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
112    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
113    ; GFX10-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
114    ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
115    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
116    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
117    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
118    ; GFX10: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
119    ; GFX10: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
120    %0:vgpr(s32) = COPY $vgpr0
121    %1:vgpr(s32) = COPY $vgpr1
122    %2:vgpr(s32) = COPY $vgpr2
123    %3:vgpr(s32) = G_AND %0, %1
124    %4:vgpr(s32) = G_OR %2, %3
125    S_ENDPGM 0, implicit %4
126...
127
128---
129
130name:            and_or_s32_sgpr_sgpr_vgpr
131legalized:       true
132regBankSelected: true
133tracksRegLiveness: true
134
135body: |
136  bb.0:
137    liveins: $sgpr0, $sgpr1, $vgpr0
138    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
139    ; GFX8: liveins: $sgpr0, $sgpr1, $vgpr0
140    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
141    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
142    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
143    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
144    ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
145    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
146    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
147    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
148    ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0
149    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
150    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
151    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
152    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
153    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
154    ; GFX9: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
155    ; GFX9: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
156    ; GFX10-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
157    ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0
158    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
159    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
160    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
161    ; GFX10: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
162    ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
163    ; GFX10: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
164    ; GFX10: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
165    %0:sgpr(s32) = COPY $sgpr0
166    %1:sgpr(s32) = COPY $sgpr1
167    %2:vgpr(s32) = COPY $vgpr0
168    %3:sgpr(s32) = G_AND %0, %1
169    %4:vgpr(s32) = COPY %3
170    %5:vgpr(s32) = G_OR %4, %2
171    S_ENDPGM 0, implicit %5
172...
173