1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
5# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
6
7---
8name:            sub_s32
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
16
17
18    ; GFX6-LABEL: name: sub_s32
19    ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
20    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
21    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
22    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
23    ; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
24    ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_SUB_CO_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
25    ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_SUB_CO_U32_e64 [[S_SUB_I32_]], %7, 0, implicit $exec
26    ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_SUB_CO_U32_e64 %8, [[COPY2]], 0, implicit $exec
27    ; GFX6: S_ENDPGM 0, implicit %9
28    ; GFX9-LABEL: name: sub_s32
29    ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
30    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
31    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
32    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
33    ; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
34    ; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
35    ; GFX9: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_I32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
36    ; GFX9: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
37    ; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
38    ; GFX10-LABEL: name: sub_s32
39    ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
40    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
41    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
42    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
43    ; GFX10: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def $scc
44    ; GFX10: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec
45    ; GFX10: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_I32_]], [[V_SUB_U32_e64_]], 0, implicit $exec
46    ; GFX10: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec
47    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]
48    %0:sgpr(s32) = COPY $sgpr0
49    %1:sgpr(s32) = COPY $sgpr1
50    %2:vgpr(s32) = COPY $vgpr0
51    %3:vgpr(p1) = COPY $vgpr3_vgpr4
52    %4:sgpr(s32) = G_CONSTANT i32 1
53    %5:sgpr(s32) = G_CONSTANT i32 4096
54
55    ; sub ss
56    %6:sgpr(s32) = G_SUB %0, %1
57
58    ; sub vs
59    %7:vgpr(s32) = G_SUB %2, %6
60
61    ; sub sv
62    %8:vgpr(s32) = G_SUB %6, %7
63
64    ; sub vv
65    %9:vgpr(s32) = G_SUB %8, %2
66
67    S_ENDPGM 0, implicit %9
68
69...
70