1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
4# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
5
6---
7
8name: trunc_sgpr_v2s32_to_v2s16
9legalized:       true
10regBankSelected: true
11
12body: |
13  bb.0:
14    liveins: $sgpr0_sgpr1
15    ; GFX6-LABEL: name: trunc_sgpr_v2s32_to_v2s16
16    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
17    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
18    ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
19    ; GFX6: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def $scc
20    ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
21    ; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
22    ; GFX6: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def $scc
23    ; GFX6: S_ENDPGM 0, implicit [[S_OR_B32_]]
24    ; GFX8-LABEL: name: trunc_sgpr_v2s32_to_v2s16
25    ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
26    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
27    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
28    ; GFX8: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def $scc
29    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
30    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
31    ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def $scc
32    ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
33    %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
34    %1:sgpr(<2 x s16>) = G_TRUNC %0
35    S_ENDPGM 0, implicit %1
36...
37
38---
39
40name: trunc_vgpr_v2s32_to_v2s16
41legalized:       true
42regBankSelected: true
43
44body: |
45  bb.0:
46    liveins: $vgpr0_vgpr1
47    ; GFX6-LABEL: name: trunc_vgpr_v2s32_to_v2s16
48    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
49    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
50    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
51    ; GFX6: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[COPY2]], implicit $exec
52    ; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
53    ; GFX6: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
54    ; GFX6: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_LSHLREV_B32_e64_]], [[V_AND_B32_e64_]], implicit $exec
55    ; GFX6: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
56    ; GFX8-LABEL: name: trunc_vgpr_v2s32_to_v2s16
57    ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
58    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
59    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
60    ; GFX8: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[COPY2]], 0, 5, 2, 4, implicit $exec, implicit [[COPY1]](tied-def 0)
61    ; GFX8: S_ENDPGM 0, implicit [[V_MOV_B32_sdwa]]
62    %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
63    %1:vgpr(<2 x s16>) = G_TRUNC %0
64    S_ENDPGM 0, implicit %1
65...
66