1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
3
4; Check that we correctly skip over disabled inputs
5define amdgpu_ps void @disabled_input(float inreg %arg0, float %psinput0, float %psinput1) #1 {
6  ; CHECK-LABEL: name: disabled_input
7  ; CHECK: bb.1.main_body:
8  ; CHECK:   liveins: $sgpr2, $vgpr0
9  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
10  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
11  ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
12  ; CHECK:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
13  ; CHECK:   S_ENDPGM 0
14main_body:
15  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
16  ret void
17}
18
19define amdgpu_ps void @disabled_input_struct(float inreg %arg0, { float, float } %psinput0, float %psinput1) #1 {
20  ; CHECK-LABEL: name: disabled_input_struct
21  ; CHECK: bb.1.main_body:
22  ; CHECK:   liveins: $sgpr2, $vgpr0
23  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
24  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
25  ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
26  ; CHECK:   [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
27  ; CHECK:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
28  ; CHECK:   S_ENDPGM 0
29main_body:
30  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
31  ret void
32}
33
34define amdgpu_ps float @vgpr_return(i32 %vgpr) {
35  ; CHECK-LABEL: name: vgpr_return
36  ; CHECK: bb.1 (%ir-block.0):
37  ; CHECK:   liveins: $vgpr0
38  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
39  ; CHECK:   $vgpr0 = COPY [[COPY]](s32)
40  ; CHECK:   SI_RETURN_TO_EPILOG implicit $vgpr0
41  %cast = bitcast i32 %vgpr to float
42  ret float %cast
43}
44
45define amdgpu_ps i32 @sgpr_return_i32(i32 %vgpr) {
46  ; CHECK-LABEL: name: sgpr_return_i32
47  ; CHECK: bb.1 (%ir-block.0):
48  ; CHECK:   liveins: $vgpr0
49  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
50  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
51  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
52  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0
53  ret i32 %vgpr
54}
55
56define amdgpu_ps i64 @sgpr_return_i64(i64 %vgpr) {
57  ; CHECK-LABEL: name: sgpr_return_i64
58  ; CHECK: bb.1 (%ir-block.0):
59  ; CHECK:   liveins: $vgpr0, $vgpr1
60  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
61  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
62  ; CHECK:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
63  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
64  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
65  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
66  ; CHECK:   [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
67  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
68  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
69  ret i64 %vgpr
70}
71
72define amdgpu_ps <2 x i32> @sgpr_return_v2i32(<2 x i32> %vgpr) {
73  ; CHECK-LABEL: name: sgpr_return_v2i32
74  ; CHECK: bb.1 (%ir-block.0):
75  ; CHECK:   liveins: $vgpr0, $vgpr1
76  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
77  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
78  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
79  ; CHECK:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)
80  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)
81  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
82  ; CHECK:   [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
83  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
84  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
85  ret <2 x i32> %vgpr
86}
87
88define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1) {
89  ; CHECK-LABEL: name: sgpr_struct_return_i32_i32
90  ; CHECK: bb.1 (%ir-block.0):
91  ; CHECK:   liveins: $vgpr0, $vgpr1
92  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
93  ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
94  ; CHECK:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
95  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)
96  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
97  ; CHECK:   [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
98  ; CHECK:   $sgpr1 = COPY [[INT1]](s32)
99  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
100  %insertvalue0 = insertvalue { i32, i32 } undef, i32 %vgpr0, 0
101  %value = insertvalue { i32, i32 } %insertvalue0, i32 %vgpr1, 1
102  ret { i32, i32 } %value
103}
104
105declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)  #0
106
107attributes #0 = { nounwind }
108attributes #1 = { "InitialPSInputAddr"="0x00002" }
109