1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
3
4--- |
5
6  define i32 @widen_load_range0_tbaa(i24 addrspace(1)* %ptr) {
7    %load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
8    %zext = zext i24 %load to i32
9    ret i32 %zext
10  }
11
12  define i32 @widen_load_range1_tbaa(i24 addrspace(1)* %ptr) {
13    %load = load i24, i24 addrspace(1)* %ptr, !range !0, !tbaa !1
14    %zext = zext i24 %load to i32
15    ret i32 %zext
16  }
17
18  define i32 @widen_load_tbaa0(i24 addrspace(1)* %ptr) {
19    %load = load i24, i24 addrspace(1)* %ptr, !tbaa !1
20    %zext = zext i24 %load to i32
21    ret i32 %zext
22  }
23
24  define i32 @widen_load_tbaa1(i24 addrspace(1)* %ptr) {
25    %load = load i24, i24 addrspace(1)* %ptr, !tbaa !1
26    %zext = zext i24 %load to i32
27    ret i32 %zext
28  }
29
30  !0 = !{i24 0, i24 1048575}
31  !1 = !{!"omnipotent char", !2}
32  !2 = !{!"Simple C/C++ TBAA"}
33...
34
35# Make sure range metadata is not preserved when widening loads, but
36# tbaa is.
37---
38name: widen_load_range0_tbaa
39body: |
40  bb.0:
41    liveins: $vgpr0_vgpr1
42    ; SI-LABEL: name: widen_load_range0_tbaa
43    ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
44    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
45    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
46    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
47    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
48    ; SI: $vgpr0 = COPY [[AND]](s32)
49    %0:_(p1) = COPY $vgpr0_vgpr1
50    %1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
51    %2:_(s32) = G_ZEXT %1
52    $vgpr0 = COPY %2
53
54...
55
56# Result register type already matches the widened memory type.
57---
58name: widen_load_range1_tbaa
59body: |
60  bb.0:
61    liveins: $vgpr0_vgpr1
62    ; SI-LABEL: name: widen_load_range1_tbaa
63    ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
64    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
65    ; SI: $vgpr0 = COPY [[LOAD]](s32)
66    %0:_(p1) = COPY $vgpr0_vgpr1
67    %1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
68    $vgpr0 = COPY %1
69
70...
71---
72name: widen_load_tbaa0
73body: |
74  bb.0:
75    liveins: $vgpr0_vgpr1
76    ; SI-LABEL: name: widen_load_tbaa0
77    ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
78    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
79    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
80    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
81    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
82    ; SI: $vgpr0 = COPY [[AND]](s32)
83    %0:_(p1) = COPY $vgpr0_vgpr1
84    %1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
85    %2:_(s32) = G_ZEXT %1
86    $vgpr0 = COPY %2
87
88...
89
90# Result register type already matches the widened memory type.
91---
92name: widen_load_tbaa1
93body: |
94  bb.0:
95    liveins: $vgpr0_vgpr1
96    ; SI-LABEL: name: widen_load_tbaa1
97    ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
98    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
99    ; SI: $vgpr0 = COPY [[LOAD]](s32)
100    %0:_(p1) = COPY $vgpr0_vgpr1
101    %1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
102    $vgpr0 = COPY %1
103
104...
105