1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @test_wave64(i32 %arg0, [8 x i32], i64 %saved) {
5; GCN-LABEL: test_wave64:
6; GCN:       ; %bb.0: ; %entry
7; GCN-NEXT:    s_load_dword s2, s[4:5], 0x0
8; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xa
9; GCN-NEXT:    s_waitcnt lgkmcnt(0)
10; GCN-NEXT:    s_cmp_eq_u32 s2, 0
11; GCN-NEXT:    s_cselect_b32 s2, 1, 0
12; GCN-NEXT:    s_and_b32 s2, 1, s2
13; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, s2
14; GCN-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
15; GCN-NEXT:    v_mov_b32_e32 v0, s0
16; GCN-NEXT:    v_mov_b32_e32 v1, s1
17; GCN-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
18; GCN-NEXT:    s_endpgm
19entry:
20  %cond = icmp eq i32 %arg0, 0
21  %break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved)
22  store volatile i64 %break, i64 addrspace(1)* undef
23  ret void
24}
25
26declare i64 @llvm.amdgcn.if.break.i64(i1, i64)
27