1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
4
5define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, i16 %t, i16 %r) {
6; GFX9-LABEL: load_3d_v4f32_xyzw:
7; GFX9:       ; %bb.0:
8; GFX9-NEXT:    s_mov_b32 s0, s2
9; GFX9-NEXT:    s_mov_b32 s2, s4
10; GFX9-NEXT:    s_mov_b32 s4, s6
11; GFX9-NEXT:    s_mov_b32 s6, s8
12; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
13; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
14; GFX9-NEXT:    s_lshl_b32 s8, s0, 16
15; GFX9-NEXT:    s_mov_b32 s1, s3
16; GFX9-NEXT:    s_mov_b32 s3, s5
17; GFX9-NEXT:    s_mov_b32 s5, s7
18; GFX9-NEXT:    v_and_or_b32 v0, v0, v3, v1
19; GFX9-NEXT:    s_mov_b32 s7, s9
20; GFX9-NEXT:    v_and_or_b32 v1, v2, v3, s8
21; GFX9-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
22; GFX9-NEXT:    s_waitcnt vmcnt(0)
23; GFX9-NEXT:    ; return to shader part epilog
24;
25; GFX10-LABEL: load_3d_v4f32_xyzw:
26; GFX10:       ; %bb.0:
27; GFX10-NEXT:    v_mov_b32_e32 v3, 0xffff
28; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
29; GFX10-NEXT:    s_mov_b32 s0, s2
30; GFX10-NEXT:    s_mov_b32 s2, s4
31; GFX10-NEXT:    s_mov_b32 s4, s6
32; GFX10-NEXT:    s_mov_b32 s6, s8
33; GFX10-NEXT:    s_lshl_b32 s8, s0, 16
34; GFX10-NEXT:    v_and_or_b32 v0, v0, v3, v1
35; GFX10-NEXT:    v_and_or_b32 v1, v2, v3, s8
36; GFX10-NEXT:    s_mov_b32 s1, s3
37; GFX10-NEXT:    s_mov_b32 s3, s5
38; GFX10-NEXT:    s_mov_b32 s5, s7
39; GFX10-NEXT:    s_mov_b32 s7, s9
40; GFX10-NEXT:    image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
41; GFX10-NEXT:    s_waitcnt vmcnt(0)
42; GFX10-NEXT:    ; return to shader part epilog
43  %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
44  ret <4 x float> %v
45}
46
47define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i16 %s, i16 %t, i16 %r) {
48; GFX9-LABEL: load_3d_v4f32_xyzw_tfe:
49; GFX9:       ; %bb.0:
50; GFX9-NEXT:    s_mov_b32 s0, s2
51; GFX9-NEXT:    s_mov_b32 s2, s4
52; GFX9-NEXT:    s_mov_b32 s4, s6
53; GFX9-NEXT:    s_mov_b32 s6, s8
54; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
55; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
56; GFX9-NEXT:    s_lshl_b32 s8, s0, 16
57; GFX9-NEXT:    s_mov_b32 s1, s3
58; GFX9-NEXT:    s_mov_b32 s3, s5
59; GFX9-NEXT:    s_mov_b32 s5, s7
60; GFX9-NEXT:    v_and_or_b32 v0, v0, v3, v1
61; GFX9-NEXT:    s_mov_b32 s7, s9
62; GFX9-NEXT:    v_and_or_b32 v1, v2, v3, s8
63; GFX9-NEXT:    image_load v[0:4], v[0:1], s[0:7] dmask:0xf unorm a16 tfe
64; GFX9-NEXT:    v_mov_b32_e32 v5, 0
65; GFX9-NEXT:    s_waitcnt vmcnt(0)
66; GFX9-NEXT:    global_store_dword v5, v4, s[10:11]
67; GFX9-NEXT:    s_waitcnt vmcnt(0)
68; GFX9-NEXT:    ; return to shader part epilog
69;
70; GFX10-LABEL: load_3d_v4f32_xyzw_tfe:
71; GFX10:       ; %bb.0:
72; GFX10-NEXT:    v_mov_b32_e32 v3, 0xffff
73; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
74; GFX10-NEXT:    s_mov_b32 s0, s2
75; GFX10-NEXT:    s_mov_b32 s2, s4
76; GFX10-NEXT:    s_mov_b32 s4, s6
77; GFX10-NEXT:    s_mov_b32 s6, s8
78; GFX10-NEXT:    s_lshl_b32 s8, s0, 16
79; GFX10-NEXT:    v_and_or_b32 v0, v0, v3, v1
80; GFX10-NEXT:    v_and_or_b32 v1, v2, v3, s8
81; GFX10-NEXT:    s_mov_b32 s1, s3
82; GFX10-NEXT:    s_mov_b32 s3, s5
83; GFX10-NEXT:    s_mov_b32 s5, s7
84; GFX10-NEXT:    s_mov_b32 s7, s9
85; GFX10-NEXT:    v_mov_b32_e32 v5, 0
86; GFX10-NEXT:    image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
87; GFX10-NEXT:    s_waitcnt vmcnt(0)
88; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
89; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
90; GFX10-NEXT:    ; return to shader part epilog
91  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0)
92  %v.vec = extractvalue { <4 x float>, i32 } %v, 0
93  %v.err = extractvalue { <4 x float>, i32 } %v, 1
94  store i32 %v.err, i32 addrspace(1)* %out, align 4
95  ret <4 x float> %v.vec
96}
97
98define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i16 %s, i16 %t, i16 %r) {
99; GFX9-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
100; GFX9:       ; %bb.0:
101; GFX9-NEXT:    s_mov_b32 s0, s2
102; GFX9-NEXT:    s_mov_b32 s2, s4
103; GFX9-NEXT:    s_mov_b32 s4, s6
104; GFX9-NEXT:    s_mov_b32 s6, s8
105; GFX9-NEXT:    v_mov_b32_e32 v3, 0xffff
106; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
107; GFX9-NEXT:    s_lshl_b32 s8, s0, 16
108; GFX9-NEXT:    s_mov_b32 s1, s3
109; GFX9-NEXT:    s_mov_b32 s3, s5
110; GFX9-NEXT:    s_mov_b32 s5, s7
111; GFX9-NEXT:    v_and_or_b32 v0, v0, v3, v1
112; GFX9-NEXT:    s_mov_b32 s7, s9
113; GFX9-NEXT:    v_and_or_b32 v1, v2, v3, s8
114; GFX9-NEXT:    image_load v[0:4], v[0:1], s[0:7] dmask:0xf unorm a16 tfe lwe
115; GFX9-NEXT:    v_mov_b32_e32 v5, 0
116; GFX9-NEXT:    s_waitcnt vmcnt(0)
117; GFX9-NEXT:    global_store_dword v5, v4, s[10:11]
118; GFX9-NEXT:    s_waitcnt vmcnt(0)
119; GFX9-NEXT:    ; return to shader part epilog
120;
121; GFX10-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
122; GFX10:       ; %bb.0:
123; GFX10-NEXT:    v_mov_b32_e32 v3, 0xffff
124; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
125; GFX10-NEXT:    s_mov_b32 s0, s2
126; GFX10-NEXT:    s_mov_b32 s2, s4
127; GFX10-NEXT:    s_mov_b32 s4, s6
128; GFX10-NEXT:    s_mov_b32 s6, s8
129; GFX10-NEXT:    s_lshl_b32 s8, s0, 16
130; GFX10-NEXT:    v_and_or_b32 v0, v0, v3, v1
131; GFX10-NEXT:    v_and_or_b32 v1, v2, v3, s8
132; GFX10-NEXT:    s_mov_b32 s1, s3
133; GFX10-NEXT:    s_mov_b32 s3, s5
134; GFX10-NEXT:    s_mov_b32 s5, s7
135; GFX10-NEXT:    s_mov_b32 s7, s9
136; GFX10-NEXT:    v_mov_b32_e32 v5, 0
137; GFX10-NEXT:    image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
138; GFX10-NEXT:    s_waitcnt vmcnt(0)
139; GFX10-NEXT:    global_store_dword v5, v4, s[10:11]
140; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
141; GFX10-NEXT:    ; return to shader part epilog
142  %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 3, i32 0)
143  %v.vec = extractvalue { <4 x float>, i32 } %v, 0
144  %v.err = extractvalue { <4 x float>, i32 } %v, 1
145  store i32 %v.err, i32 addrspace(1)* %out, align 4
146  ret <4 x float> %v.vec
147}
148
149declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
150declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 immarg, i16, i16, i16, <8 x i32>, i32 immarg, i32 immarg) #0
151
152attributes #0 = { nounwind readonly }
153