1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5--- 6name: interp_p2_f16_sss 7legalized: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0, $sgpr1, $sgpr2 13 14 ; CHECK-LABEL: name: interp_p2_f16_sss 15 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 16 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 17 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 18 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 19 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 20 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) 21 ; CHECK: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2.f16), [[COPY3]](s32), [[COPY4]](s32), 1, 1, 1, [[COPY2]](s32) 22 %0:_(s32) = COPY $sgpr0 23 %1:_(s32) = COPY $sgpr1 24 %2:_(s32) = COPY $sgpr2 25 %3:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2.f16), %0, %1, 1, 1, 1, %2 26... 27 28--- 29name: interp_p2_f16_ssv 30legalized: true 31tracksRegLiveness: true 32 33body: | 34 bb.0: 35 liveins: $sgpr0, $sgpr1, $vgpr0 36 ; CHECK-LABEL: name: interp_p2_f16_ssv 37 ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0 38 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 39 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 40 ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 41 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 42 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) 43 ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec 44 ; CHECK: [[INT:%[0-9]+]]:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2.f16), [[COPY3]](s32), [[COPY4]](s32), 1, 1, 1, [[V_READFIRSTLANE_B32_]](s32) 45 %0:_(s32) = COPY $sgpr0 46 %1:_(s32) = COPY $sgpr1 47 %2:_(s32) = COPY $vgpr0 48 %3:_(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p2.f16), %0, %1, 1, 1, 1, %2 49... 50