1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
4
5---
6name: readlane_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: readlane_ss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
15    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
16    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
17    %0:_(s32) = COPY $sgpr0
18    %1:_(s32) = COPY $sgpr1
19    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
20...
21
22---
23name: readlane_vs
24legalized: true
25
26body: |
27  bb.0:
28    liveins: $vgpr0, $sgpr0
29    ; CHECK-LABEL: name: readlane_vs
30    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
32    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[COPY1]](s32)
33    %0:_(s32) = COPY $vgpr0
34    %1:_(s32) = COPY $sgpr0
35    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
36...
37
38---
39name: readlane_vv
40legalized: true
41
42body: |
43  bb.0:
44    liveins: $vgpr0, $vgpr1
45    ; CHECK-LABEL: name: readlane_vv
46    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
47    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
48    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
49    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
50    %0:_(s32) = COPY $vgpr0
51    %1:_(s32) = COPY $vgpr1
52    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
53...
54
55---
56name: readlane_sv
57legalized: true
58
59body: |
60  bb.0:
61    liveins: $vgpr0, $sgpr0
62    ; CHECK-LABEL: name: readlane_sv
63    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
64    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
65    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
66    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
67    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
68    %0:_(s32) = COPY $sgpr0
69    %1:_(s32) = COPY $vgpr0
70    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
71...
72
73---
74name: readlane_aa
75legalized: true
76
77body: |
78  bb.0:
79    liveins: $agpr0, $agpr1
80    ; CHECK-LABEL: name: readlane_aa
81    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
82    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
83    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
84    ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
85    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
86    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
87    ; CHECK: S_ENDPGM 0, implicit [[INT]](s32)
88    %0:_(s32) = COPY $agpr0
89    %1:_(s32) = COPY $agpr1
90    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
91    S_ENDPGM 0, implicit %2
92...
93
94---
95name: readlane_as
96legalized: true
97
98body: |
99  bb.0:
100    liveins: $agpr0, $sgpr0
101    ; CHECK-LABEL: name: readlane_as
102    ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
103    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
104    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
105    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
106    %0:_(s32) = COPY $agpr0
107    %1:_(s32) = COPY $sgpr0
108    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
109...
110
111---
112name: readlane_sa
113legalized: true
114
115body: |
116  bb.0:
117    liveins: $agpr0, $sgpr0
118    ; CHECK-LABEL: name: readlane_sa
119    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
120    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
121    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
122    ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
123    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
124    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
125    %0:_(s32) = COPY $sgpr0
126    %1:_(s32) = COPY $agpr0
127    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
128...
129
130---
131name: readlane_va
132legalized: true
133
134body: |
135  bb.0:
136    liveins: $vgpr0, $agpr0
137    ; CHECK-LABEL: name: readlane_va
138    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
139    ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
140    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
141    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec
142    ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
143    %0:_(s32) = COPY $vgpr0
144    %1:_(s32) = COPY $agpr0
145    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
146...
147