1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=regbankselect %s -o - | FileCheck -check-prefix=SI %s
3
4--- |
5
6  define amdgpu_ps i96 @split_smrd_load_range(i96 addrspace(4)* %ptr) {
7    %load = load i96, i96 addrspace(4)* %ptr, !range !0
8    ret i96 %load
9  }
10
11  define amdgpu_ps <3 x i32> @split_smrd_load_tbaa(<3 x i32> addrspace(4)* %ptr) {
12    %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, !tbaa !1
13    ret <3 x i32> %load
14  }
15
16  !0 = !{i96 0, i96 9223372036854775808}
17  !1 = !{!"omnipotent char", !2}
18  !2 = !{!"Simple C/C++ TBAA"}
19...
20
21# Make sure range metadata is not preserved when widening loads, but
22# tbaa is.
23
24---
25name: split_smrd_load_range
26legalized: true
27body: |
28  bb.0:
29    liveins: $sgpr0_sgpr1
30
31    ; SI-LABEL: name: split_smrd_load_range
32    ; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
33    ; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, addrspace 4)
34    ; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
35    ; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
36    ; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, addrspace 4)
37    ; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
38    ; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
39    ; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
40    ; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
41    %0:_(p4) = COPY $sgpr0_sgpr1
42    %1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !range !0)
43    $sgpr0_sgpr1_sgpr2 = COPY %1
44
45...
46
47---
48name: split_smrd_load_tbaa
49legalized: true
50body: |
51  bb.0:
52    liveins: $sgpr0_sgpr1
53
54    ; SI-LABEL: name: split_smrd_load_tbaa
55    ; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
56    ; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, !tbaa !2, addrspace 4)
57    ; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
58    ; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
59    ; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, !tbaa !2, addrspace 4)
60    ; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
61    ; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
62    ; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
63    ; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
64    %0:_(p4) = COPY $sgpr0_sgpr1
65    %1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !tbaa !1)
66    $sgpr0_sgpr1_sgpr2 = COPY %1
67
68...
69