1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s 3 4define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(float addrspace(1)* %p) #4 { 5; GCN-LABEL: test_mul24_knownbits_kernel: 6; GCN: ; %bb.0: ; %entry 7; GCN-NEXT: v_and_b32_e32 v0, 3, v0 8; GCN-NEXT: v_mul_i32_i24_e32 v0, -5, v0 9; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 10; GCN-NEXT: v_and_b32_e32 v0, 0xffffffe0, v0 11; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 12; GCN-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] 13; GCN-NEXT: s_waitcnt lgkmcnt(0) 14; GCN-NEXT: v_mov_b32_e32 v2, s1 15; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 16; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc 17; GCN-NEXT: v_mov_b32_e32 v2, 0 18; GCN-NEXT: global_store_dword v[0:1], v2, off 19; GCN-NEXT: s_endpgm 20entry: 21 %0 = tail call i32 @llvm.amdgcn.workitem.id.x() #28, !range !4 22 %tid = and i32 %0, 3 23 %1 = mul nsw i32 %tid, -5 24 %v1 = and i32 %1, -32 25 %v2 = sext i32 %v1 to i64 26 %v3 = getelementptr inbounds float, float addrspace(1)* %p, i64 %v2 27 store float 0.000, float addrspace(1)* %v3, align 4 28 ret void 29} 30 31; Function Attrs: nounwind readnone speculatable 32declare i32 @llvm.amdgcn.workitem.id.x() #20 33 34!4 = !{i32 0, i32 1024} 35