1; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
4
5; This pixel shader does not use the result of its interpolation, so it would
6; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests
7; the workaround that ensures that an interpolation mode is also set in PSEnable.
8; GCN-LABEL: {{^}}amdpal_psenable:
9; GCN:         .amdgpu_pal_metadata
10; GCN-NEXT: ---
11; GCN-NEXT: amdpal.pipelines:
12; GCN-NEXT:   - .hardware_stages:
13; GCN-NEXT:       .ps:
14; GCN-NEXT:         .entry_point:    amdpal_psenable
15; GCN-NEXT:         .scratch_memory_size: 0
16; GCN:     .registers:
17; GCN-NEXT:       0x2c0a (SPI_SHADER_PGM_RSRC1_PS):
18; GCN-NEXT:       0x2c0b (SPI_SHADER_PGM_RSRC2_PS):
19; GCN-NEXT:       0xa1b3 (SPI_PS_INPUT_ENA): 0x2
20; GCN-NEXT:       0xa1b4 (SPI_PS_INPUT_ADDR): 0x2
21; GCN-NEXT: ...
22; GCN-NEXT:         .end_amdgpu_pal_metadata
23define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 {
24  %inst23 = extractelement <2 x float> %pos, i32 0
25  %inst24 = extractelement <2 x float> %pos, i32 1
26  %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0)
27  %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0)
28  ret void
29}
30
31declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
32declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
33
34attributes #6 = { nounwind "InitialPSInputAddr"="2" }
35