1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefixes=PAL,CI --enable-var-scope %s
2; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga | FileCheck --check-prefixes=PAL,VI --enable-var-scope %s
3
4; PAL-NOT: .AMDGPU.config
5; PAL-LABEL: {{^}}simple:
6define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
7entry:
8  store i32 0, i32 addrspace(1)* %out
9  ret void
10}
11
12; Check code sequence for amdpal use of scratch for alloca. This is the case
13; where the high half of the address comes from s_getpc.
14
15; PAL-LABEL: {{^}}scratch:
16; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
17; PAL: s_mov_b32 s[[GITPTR]], s0
18; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
19; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
20
21define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
22entry:
23  %v = alloca [2 x i32], addrspace(5)
24  %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
25  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
26  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
27  %x = load i32, i32 addrspace(5)* %e
28  store i32 %x, i32 addrspace(5)* %out
29  ret void
30}
31
32; Check code sequence for amdpal use of scratch for alloca. This is the case
33; where the amdgpu-git-ptr-high function attribute gives the high half of the
34; address to use.
35; Looks like you can't do arithmetic on a filecheck variable, so we can't test
36; that the s_movk_i32 is into a reg that is one more than the following
37; s_mov_b32.
38
39; PAL-LABEL: {{^}}scratch2:
40; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
41; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
42; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
43; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
44
45define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
46entry:
47  %v = alloca [2 x i32], addrspace(5)
48  %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
49  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
50  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
51  %x = load i32, i32 addrspace(5)* %e
52  store i32 %x, i32 addrspace(5)* %out
53  ret void
54}
55
56; Check code sequence for amdpal use of scratch for alloca in a compute shader.
57; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
58; 0 in a graphics shader.
59; Prior to GCN3 s_load_dword offsets are dwords, so the offset will be 0x4.
60
61; PAL-LABEL: {{^}}scratch2_cs:
62; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
63; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
64; CI: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x4
65; VI: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10
66; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
67
68define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
69entry:
70  %v = alloca [3 x i32], addrspace(5)
71  %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
72  %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
73  store i32 %extra, i32 addrspace(5)* %v0
74  %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
75  %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*
76  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
77  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
78  %x = load i32, i32 addrspace(5)* %e
79  %xf = bitcast i32 %x to float
80  call void @llvm.amdgcn.raw.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i32 0)
81  ret void
82}
83
84attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
85
86declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg)
87
88
89; PAL:         .amdgpu_pal_metadata
90; PAL-NEXT: ---
91; PAL-NEXT: amdpal.pipelines:
92; PAL-NEXT:   - .hardware_stages:
93; PAL-NEXT:       .cs:
94; PAL-NEXT:         .entry_point:    scratch2_cs
95; PAL-NEXT:         .scratch_memory_size: 0x10
96; PAL-NEXT:         .sgpr_count:     0x
97; PAL-NEXT:         .vgpr_count:     0x
98