1; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
2; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
3; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
5
6; GCN-LABEL: {{^}}scalar_andn2_i32_one_use
7; GCN: s_andn2_b32
8define amdgpu_kernel void @scalar_andn2_i32_one_use(
9    i32 addrspace(1)* %r0, i32 %a, i32 %b) {
10entry:
11  %nb = xor i32 %b, -1
12  %r0.val = and i32 %a, %nb
13  store i32 %r0.val, i32 addrspace(1)* %r0
14  ret void
15}
16
17; GCN-LABEL: {{^}}scalar_andn2_i64_one_use
18; GCN: s_andn2_b64
19define amdgpu_kernel void @scalar_andn2_i64_one_use(
20    i64 addrspace(1)* %r0, i64 %a, i64 %b) {
21entry:
22  %nb = xor i64 %b, -1
23  %r0.val = and i64 %a, %nb
24  store i64 %r0.val, i64 addrspace(1)* %r0
25  ret void
26}
27
28; GCN-LABEL: {{^}}scalar_orn2_i32_one_use
29; GCN: s_orn2_b32
30define amdgpu_kernel void @scalar_orn2_i32_one_use(
31    i32 addrspace(1)* %r0, i32 %a, i32 %b) {
32entry:
33  %nb = xor i32 %b, -1
34  %r0.val = or i32 %a, %nb
35  store i32 %r0.val, i32 addrspace(1)* %r0
36  ret void
37}
38
39; GCN-LABEL: {{^}}scalar_orn2_i64_one_use
40; GCN: s_orn2_b64
41define amdgpu_kernel void @scalar_orn2_i64_one_use(
42    i64 addrspace(1)* %r0, i64 %a, i64 %b) {
43entry:
44  %nb = xor i64 %b, -1
45  %r0.val = or i64 %a, %nb
46  store i64 %r0.val, i64 addrspace(1)* %r0
47  ret void
48}
49
50; GCN-LABEL: {{^}}vector_andn2_i32_s_v_one_use
51; GCN: v_not_b32
52; GCN: v_and_b32
53define amdgpu_kernel void @vector_andn2_i32_s_v_one_use(
54    i32 addrspace(1)* %r0, i32 %s) {
55entry:
56  %v = call i32 @llvm.amdgcn.workitem.id.x() #1
57  %not = xor i32 %v, -1
58  %r0.val = and i32 %s, %not
59  store i32 %r0.val, i32 addrspace(1)* %r0
60  ret void
61}
62
63; GCN-LABEL: {{^}}vector_andn2_i32_v_s_one_use
64; GCN: s_not_b32
65; GCN: v_and_b32
66define amdgpu_kernel void @vector_andn2_i32_v_s_one_use(
67    i32 addrspace(1)* %r0, i32 %s) {
68entry:
69  %v = call i32 @llvm.amdgcn.workitem.id.x() #1
70  %not = xor i32 %s, -1
71  %r0.val = and i32 %v, %not
72  store i32 %r0.val, i32 addrspace(1)* %r0
73  ret void
74}
75
76; GCN-LABEL: {{^}}vector_orn2_i32_s_v_one_use
77; GCN: v_not_b32
78; GCN: v_or_b32
79define amdgpu_kernel void @vector_orn2_i32_s_v_one_use(
80    i32 addrspace(1)* %r0, i32 %s) {
81entry:
82  %v = call i32 @llvm.amdgcn.workitem.id.x() #1
83  %not = xor i32 %v, -1
84  %r0.val = or i32 %s, %not
85  store i32 %r0.val, i32 addrspace(1)* %r0
86  ret void
87}
88
89; GCN-LABEL: {{^}}vector_orn2_i32_v_s_one_use
90; GCN: s_not_b32
91; GCN: v_or_b32
92define amdgpu_kernel void @vector_orn2_i32_v_s_one_use(
93    i32 addrspace(1)* %r0, i32 %s) {
94entry:
95  %v = call i32 @llvm.amdgcn.workitem.id.x() #1
96  %not = xor i32 %s, -1
97  %r0.val = or i32 %v, %not
98  store i32 %r0.val, i32 addrspace(1)* %r0
99  ret void
100}
101
102; Function Attrs: nounwind readnone
103declare i32 @llvm.amdgcn.workitem.id.x() #0
104