1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI,SICI,SICIVI,GCN %s
2; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SICI,CIVI,SICIVI,GCN %s
3; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,SICIVI,GFX89,GCN %s
4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX89,GCN %s
5
6; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset:
7; GFX9-NOT: m0
8; SICIVI-DAG: s_mov_b32 m0
9
10; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
11; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x1c
12; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
13; GFX89-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x70
14; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
15; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
16; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
17; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
18; GCN: s_endpgm
19define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, [8 x i32], i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
20  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
21  %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
22  %result = extractvalue { i32, i1 } %pair, 0
23  store i32 %result, i32 addrspace(1)* %out, align 4
24  ret void
25}
26
27; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset:
28; GFX9-NOT: m0
29; SICIVI-DAG: s_mov_b32 m0
30
31; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
32; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
33; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
34; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
35; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
36; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
37; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
38; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
39; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
40; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
41; GCN: [[RESULT]]
42; GCN: s_endpgm
43define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
44  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
45  %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
46  %result = extractvalue { i64, i1 } %pair, 0
47  store i64 %result, i64 addrspace(1)* %out, align 8
48  ret void
49}
50
51; GCN-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
52; GFX9-NOT: m0
53; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
54; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
55; GFX9: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
56; GCN: s_endpgm
57define amdgpu_kernel void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
58  %sub = sub i32 %a, %b
59  %add = add i32 %sub, 4
60  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
61  %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
62  %result = extractvalue { i32, i1 } %pair, 0
63  store i32 %result, i32 addrspace(1)* %out, align 4
64  ret void
65}
66
67; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i32_offset:
68; GFX9-NOT: m0
69; SICIVI-DAG: s_mov_b32 m0
70
71
72; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
73; SICI-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x12
74; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
75; GFX89-DAG: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x48
76; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
77; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
78; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
79; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
80; GCN: s_endpgm
81define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, [8 x i32], i32 %swap) nounwind {
82  %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
83  %pair = cmpxchg i32 addrspace(3)* %gep, i32 7, i32 %swap seq_cst monotonic
84  %result = extractvalue { i32, i1 } %pair, 0
85  ret void
86}
87
88; GCN-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset:
89; GFX9-NOT: m0
90; SICIVI-DAG: s_mov_b32 m0
91
92; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9
93; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
94; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
95; GFX89-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
96; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7
97; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0
98; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
99; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
100; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
101; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
102; GCN: s_endpgm
103define amdgpu_kernel void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
104  %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
105  %pair = cmpxchg i64 addrspace(3)* %gep, i64 7, i64 %swap seq_cst monotonic
106  %result = extractvalue { i64, i1 } %pair, 0
107  ret void
108}
109