1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
2; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
3
4; Make sure the code size estimate for inline asm is 12-bytes per
5; instruction, rather than 8 in previous generations.
6
7; GCN-LABEL: {{^}}long_forward_branch_gfx10only:
8; GFX9: s_cmp_eq_u32
9; GFX9-NEXT: s_cbranch_scc1
10
11; GFX10: s_cmp_eq_u32
12; GFX10-NEXT: s_cbranch_scc0
13; GFX10: s_getpc_b64
14; GFX10: s_add_u32
15; GFX10: s_addc_u32
16; GFX10: s_setpc_b64
17define amdgpu_kernel void @long_forward_branch_gfx10only(i32 addrspace(1)* %arg, i32 %cnd) #0 {
18bb0:
19  %cmp = icmp eq i32 %cnd, 0
20  br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
21
22bb2:
23    ; Estimated as 40-bytes on gfx10 (requiring a long branch), but
24    ; 16-bytes on gfx9 (allowing a short branch)
25  call void asm sideeffect
26   "v_nop_e64
27    v_nop_e64", ""() #0
28  br label %bb3
29
30bb3:
31  store volatile i32 %cnd, i32 addrspace(1)* %arg
32  ret void
33}
34