1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
3
4; CHECK-LABEL: {{^}}main:
5;
6; Test for compilation only. This generated an invalid machine instruction
7; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
8; of which were in SGPRs.
9define amdgpu_vs float @main(i32 %v) {
10main_body:
11  %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 960, i32 0)
12  %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 976, i32 0)
13  br i1 undef, label %ENDIF56, label %IF57
14
15IF57:                                             ; preds = %ENDIF
16  %v.1 = mul i32 %v, 2
17  br label %ENDIF56
18
19ENDIF56:                                          ; preds = %IF57, %ENDIF
20  %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]
21  %d1.i = bitcast float %d1 to i32
22  %cc1 = icmp eq i32 %d1.i, 0
23  br i1 %cc1, label %ENDIF59, label %IF60
24
25IF60:                                             ; preds = %ENDIF56
26  %v.3 = mul i32 %v.2, 2
27  br label %ENDIF59
28
29ENDIF59:                                          ; preds = %IF60, %ENDIF56
30  %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]
31  %d2.i = bitcast float %d2 to i32
32  %cc2 = icmp eq i32 %d2.i, 0
33  br i1 %cc2, label %ENDIF62, label %IF63
34
35IF63:                                             ; preds = %ENDIF59
36  unreachable
37
38ENDIF62:                                          ; preds = %ENDIF59
39  %r = bitcast i32 %v.4 to float
40  ret float %r
41}
42
43; Function Attrs: nounwind readnone
44declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
45
46attributes #0 = { nounwind readnone }
47attributes #1 = { readnone }
48